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| january 2008 rev 1 1/201 1 st7232ak1-auto st7232ak2-auto st7232aj1-auto st7232aj2-auto 8-bit mcu for automotive, 16 kbyte flash/rom, 10-bit adc, 4 timers, spi, sci features memories ? 8k dual voltage high density flash (hdflash) or rom with read-out protection capability. in-applicat ion programming and in-circuit programming for hdflash devices ? 384 bytes ram ? hdflash endurance: 100 cycles, data retention: 20 years at 55c clock, reset and supply management ? clock sources: crys tal/ceramic resonator oscillators and bypass for external clock ? pll for 2x frequency multiplication ? four power saving modes: halt, active halt, wait and slow interrupt management ? nested interrupt controller ? 14 interrupt vectors plus trap and reset ? 6 external interrupt lines (on 4 vectors) up to 32 i/o ports ? 32/24 multifunctional bidirectional i/o lines ? 22/17 alternate function lines ? 12/10 high sink outputs 4 timers ? main clock controller with: real time base, beep and clock-out capabilities ? configurable watchdog timer ? two 16-bit timers with: 2 input captures, 2 output compares, pwm and pulse generator modes 2 communications interfaces ? spi synchronous serial interface ? sci asynchronous serial interface 1 analog peripheral (low current coupling) ? 10-bit adc with up to 12 robust input ports instruction set ? 8-bit data manipulation ? 63 basic instructions ? 17 main addressing modes ? 8 x 8 unsigned multiply instruction development tools ? full hardware/software development package ? in-circuit testing capability lqfp44 10 x 10 lqfp32 7 x 7 table 1. device summary program memory - bytes ram (stack) - by tes operating volt. temp. range package st72f32ak1-auto flash 4k 384 (256) 3.8v to 5.5v -40c to +125c lqfp32 st72f32ak2-auto flash 8k st72f32aj1-auto flash 4k lqfp44 st72f32aj2-auto flash 8k st7232ak1-auto rom 4k lqfp32 st7232ak2-auto rom 8k st7232aj1-auto rom 4k lqfp44 st7232aj2-auto rom 8k www.st.com obsolete product(s) - obsolete product(s)
contents st7232axx-auto 2/201 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2 differences between st7232a-auto and st7232a datasheets . . . . . . . . 15 1.2.1 principal differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.2 minor content differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.3 editing and formatting differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.1 read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.5 in-circuit programming (icp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6 in-application programming (iap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.7 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.4.1 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.4.2 crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 obsolete product(s) - obsolete product(s) st7232axx-auto contents 3/201 6.5 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.5.2 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.5.3 external power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.5.4 internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.6 system integrity management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.1 servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2.2 different interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2.3 non-maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2.4 maskable sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.4 concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.6 interrupt related instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.7 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.7.1 i/o port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.8 external interrupt control register (eicr) . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.9 nested interrupts register map and reset value . . . . . . . . . . . . . . . . . . . . 53 7.10 interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.4 active halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.4.1 active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.4.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 obsolete product(s) - obsolete product(s) contents st7232axx-auto 4/201 9.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.1.4 how to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.1.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.1.6 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.1.7 using halt mode with the wdg (wdghalt option) . . . . . . . . . . . . . . . 72 10.1.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.1.9 control register (wdgcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.1.10 watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . 73 10.2 main clock controller with real-time clock and beeper (mcc/rtc) . . . . . 73 10.2.1 programmable cpu clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.2.2 clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.2.3 real-time clock timer (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.2.4 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.2.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.2.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.2.7 mcc/rtc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.2.8 mcc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.3.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.3.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.3.6 summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.3.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 obsolete product(s) - obsolete product(s) st7232axx-auto contents 5/201 10.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.4.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.4.4 clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 10.4.5 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 10.4.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 10.4.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.4.8 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.5 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.5.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.5.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.5.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.5.7 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 10.6 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.6.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.6.6 10-bit adc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.1 cpu addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.1.1 inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.1.2 immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.1.3 direct instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.1.4 indexed instructions (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . 147 11.1.5 indirect instructions (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.1.6 indirect indexed instructions (short, long) . . . . . . . . . . . . . . . . . . . . . . 148 11.1.7 relative mode instructions (direct, indirect) . . . . . . . . . . . . . . . . . . . . . 149 11.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.3 using a pre-byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 obsolete product(s) - obsolete product(s) contents st7232axx-auto 6/201 12 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.2.1 voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.2.2 current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.4.1 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.4.2 supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.4.3 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.5.1 general timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.5.2 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.5.3 crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 162 12.5.4 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.6.1 ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.6.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.7 electromagnetic compatability (emc) char acteristics . . . . . . . . . . . . . . 165 12.7.1 functional electr omagnetic susceptibility (ems) . . . . . . . . . . . . . . . . . 165 12.7.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12.7.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 167 12.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.8.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.8.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 12.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.9.1 asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 12.9.2 iccsel/v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 12.10 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 12.10.1 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 obsolete product(s) - obsolete product(s) st7232axx-auto contents 7/201 12.11 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 175 12.11.1 spi (serial peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 12.12 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 12.12.1 analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 179 12.12.2 general pcb design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 12.12.3 adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 13.3 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 14 device configuration and ordering informati on . . . . . . . . . . . . . . . . . 185 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 14.2 flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 14.2.1 flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 14.2.2 flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 14.3 rom device ordering information and transfer of customer code . . . . . 188 14.4 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14.4.2 evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14.4.3 development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14.4.4 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14.4.5 socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 193 14.5 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.1 all flash and rom devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.1.1 safe connection of osc1/osc2 pins . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.1.2 external interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.1.3 unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.1.4 clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 196 15.1.5 16-bit timer pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 15.1.6 timd set simultaneously with oc interrupt . . . . . . . . . . . . . . . . . . . . . 197 15.1.7 sci wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 15.1.8 39-pulse icc entry mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 obsolete product(s) - obsolete product(s) contents st7232axx-auto 8/201 15.2 rom devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.2.1 i/o port a and f configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.2.2 external clock source with pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 obsolete product(s) - obsolete product(s) st7232axx-auto list of tables 9/201 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 3. hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 4. sectors available in flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5. flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 6. cc register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7. st7 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 8. sicsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 9. interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 10. cpu cc register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 11. isprx interrupt vector correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 12. dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 13. eicr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 14. nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 15. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 16. active halt and halt power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 17. dr register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 18. i/o port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 19. i/o port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 20. port register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 21. effect of low power modes on i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 table 22. i/o interrup t control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 23. i/o port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 24. effect of low power modes on watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 25. wdgcr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 26. watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 27. effect of low power modes on mcc/rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 28. mcc/rtc interrupt control/wake-u p capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 29. mccsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 30. mccbcr register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 31. main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 32. effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 33. 16-bit timer interrupt control/wa ke-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 34. summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 35. cr1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 36. cr2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 37. csr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 38. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 39. effect of low power modes on spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 12 table 40. spi interrupt control/ wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 table 41. spicr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 42. spicsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 43. spi register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 44. frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 45. effect of low power modes on sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 30 table 46. sci interrupt c ontrol/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 0 table 47. scisr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 48. scicr1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 obsolete product(s) - obsolete product(s) list of tables st7232axx-auto 10/201 table 49. scicr2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 50. scibrr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 51. scierpr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 52. scietpr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 53. baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 54. sci register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 38 table 55. effect of low power modes on 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 56. adccsr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 57. adcdrh register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 58. adcdrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 59. adc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 table 60. cpu addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 44 table 61. cpu addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 62. inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 63. immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 64. instructions supporting direct, indexed, in direct and indirect indexed addressing modes 148 table 65. short instructions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 66. relative mode instructions (direct and indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 67. instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 68. instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 69. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 70. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 71. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 72. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 73. current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 74. supply current of clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 75. on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 76. general timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 77. external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 78. oscillator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 79. examples of typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 80. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 81. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 82. characteristics of dual voltage hdflash memory . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 83. electromagnetic test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 84. emi emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 85. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 table 86. latch up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 87. i/o general port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 88. output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 89. asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 90. iccsel/v pp pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 91. 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 92. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 93. 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 94. adc accuracy with v dd = 5.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 95. 32-pin lqfp mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 96. 44-pin lqfp mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 97. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 98. soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . 184 table 99. flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 100. option byte 0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 obsolete product(s) - obsolete product(s) st7232axx-auto list of tables 11/201 table 101. option byte 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 102. package selection (opt7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 103. flash user programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 104. fastrom factory coded device types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 105. rom factory coded device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 106. stmicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 107. suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 108. port a and f configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 109. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 obsolete product(s) - obsolete product(s) list of figures st7232axx-auto 12/201 list of figures figure 1. device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2. 32-pin lqfp 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 3. 44-pin lqfp package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. memory map and sector addresses of the st7232x family . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 6. typical icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7. cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8. stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 9. pll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10. clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 11. reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 12. reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 13. reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14. interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15. priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 16. concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17. nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 18. external interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 19. power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 20. slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 21. wait mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 22. active halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 23. active halt mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 24. halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 25. halt mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 26. i/o port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 27. interrupt i/o port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 28. watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 29. approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 30. exact timeout duration (t min and t max ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 31. main clock controller (mcc/rtc) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 32. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 33. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 34. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 35. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 36. counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 37. input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 38. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 39. output compare block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 40. output compare timing diagram, f timer =f cpu /2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 41. output compare timing diagram, f timer =f cpu /4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 42. one pulse mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 43. one pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 44. pulse width modulation mode timing example with 2 output compare functions . . . . . . . . 91 figure 45. pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 46. serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 figure 47. single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 48. generic ss timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 obsolete product(s) - obsolete product(s) st7232axx-auto list of figures 13/201 figure 49. hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 50. data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 51. clearing the wcol bit (wri te collision flag) so ftware sequence . . . . . . . . . . . . . . . . . . . . 111 figure 52. single master/multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 53. sci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 54. word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 55. sci baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 56. bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 57. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 58. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 59. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 60. f cpu max versus v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 61. typical i dd in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 62. typical i dd in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 63. typical i dd in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 64. typ. i dd in slow wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 65. typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 66. typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 67. integrated pll jitter vs signal frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 68. unused i/o pins configured as input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 69. typical i pu vs. v dd with v in =v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 70. typical v ol at v dd = 5v (std. ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 71. typ. v ol at v dd = 5v (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 72. typical v oh at v dd = 5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 73. typical v ol vs. v dd (std. ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 74. typical v ol vs. v dd (high-sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 75. typical v oh vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 76. reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 77. two typical applications with iccsel/v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 78. spi slave timing diagram with cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 79. spi slave timing diagram with cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 80. spi master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 81. r ain max. vs f adc with c ain = 0pf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 82. recommended c ain and r ain values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 83. typical a/d converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 84. power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 85. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 86. 32-pin lqfp outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 87. 44-pin lqfp outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 figure 88. flash commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 89. fastrom commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 90. rom commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 obsolete product(s) - obsolete product(s) introduction st7232axx-auto 14/201 1 introduction 1.1 description the st7232ak1-auto, st7232ak2-auto, st7232aj1-auto, and st7232aj2-auto devices are members of the st7 microcontroller family designed for the 5v operating range. the 32 and 44-pin devices are designed for mid-range applications all devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with flash or rom program memory. under software control, all devices can be placed in wait, slow, active halt or halt mode, reducing power consumption when the application is in idle or stand-by state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling th e design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 microcontrollers feature true bit manipulation, 8 x 8 unsigned multiplication and indirect addressing modes. figure 1. device block diagram 8-bit core alu address and data bus osc1 v pp control program (8k bytes) v dd reset port f timer a beep port a ram (384 bytes) por t c 10-bit adc v aref v ssa port b port e sci timer b port d spi v ss watchdog osc osc2 memory mcc/rtc/beep obsolete product(s) - obsolete product(s) st7232axx-auto introduction 15/201 1.2 differences between st7232a -auto and st7232a datasheets the differences between the st7232a-auto datasheet, version 1, released in january 2008 and the st7232a datasheet, version 2, released in december 2005 are listed below. differences are categorised as follows: principal differences minor content differences editing and formatting differences 1.2.1 principal differences 1. changed root part number from st7232a to st7232ak1-auto, st7232ak2-auto, st7232aj1-auto, and st7232aj2-auto throughout document 2. changed document title on page 1 3. removed 1 and 5 suffix version temperatures ranges throughout the document 4. features on page 1 : changed minimum value of data retention time (t ret ) to 20 years and changed the condition to t a = 55c 5. table 2: device pin description on page 21 : added footnote (5) 6. section 6.3: phase locked loop (pll) on page 36 : added caution regarding use of pll with an external clock 7. reset vector fetch on page 38 : added a ?caution? about the reset vector when it is not programmed 8. section 9.2.1: input modes on page 62 : amended note 3 of this section 9. section 9.3: i/o port implementation on page 66 : deleted i/o port implementation tables 10. output compare on page 85 : amended text in note 3 11. figure 41: output compare timing diagram, ftimer = fcpu/4 on page 88 : removed compare register i latch from diagram 12. section 10.6: 10-bit a/d converter (adc) on page 139 : amended text concerning the eoc bit in starting the conversion 13. table 70: current characteristics on page 155 : ? added data for the lqfp44 package to i vdd and i vss ? updated max i io values for standard i/o and high sink i/o 14. table 72: general operating conditions on page 156 : updated temperature ranges in the ?conditions? column 15. table 82: characteristics of dual voltage hdflash memory on page 164 : ? changed typical value of supply current (i dd ) to < 10a ? changed minimum value of data retention time (t ret ) to 20 years and changed the condition to t a = 55c ? changed the condition of write erase cycle (n rw ) to t a = 85c 16. section 12.7.3: absolute maximum ratings (electrical sensitivity) on page 167 : removed text concerning dynamic latch-up 17. electro-static discharge (esd) on page 167 : replaced jesd22-a114a/a115a standard with aec-q100-002/003/011 standard obsolete product(s) - obsolete product(s) introduction st7232axx-auto 16/201 18. table 85: esd absolute maximum ratings on page 167 : ? added test standards to conditions column ? changed max value of cdm from 250 v to: > 500 v to 750 v with corner pins > 750 v ? added ?class? information 19. static latch-up on page 167 : added ?aec-q100/004? standard 20. table 86: latch up results on page 167 : ? removed t a = +25c, +85c and +105c from latch-up conditions ? added aec-q100/004 test standard ? removed dynamic latch-up results ? changed ?class? information ? removed footnote 1 pertaining to class descriptions and jedec standards 21. table 87: i/o general port pin characteristics on page 168 : ? added footnote (3) and (5) ? amended footnote (4) 22. figure 76: reset pin pr otection on page 173 : removed emc protective circuitry (device works correctly without these components) 23. table 92: spi characteristics on page 175 : ? added footnote (1) and (2) ? updated max and unit information of t v (mo) ? updated min values of t h (mo) ? updated min and max values for ?data output valid? and ?data output hold? times 24. figure 80: spi master timing diagram on page 177 : modified figure to reflect changes made in table 92: spi characteristics concerning t v (mo) and t h (mo) 25. table 93: 10-bit adc characteristics on page 178 : ? removed word ?positive? from explanation of i lkg parameter ? updated footnote (2) 26. figure 83: typical a/d converter application on page 179 : changed i l 1a to i lkg 27. table 94: adc accuracy with vdd = 5.0v on page 181 : ? made the ?conditions? applicable for all parameters ? updated footnote (2) 28. table 97: thermal characteristics on page 184 : ? amended footnotes (1) and (2) ? added a value for lqfp44 29. table 99: flash option bytes on page 185 : ? changed bits 4 and 3 of option byte 0 to a default value of ?1? ? changed the oscrange bits [2:0] of option byte 1 from 111 to 011 ? added footnote 1 concerning package selection 30. updated table 100: option byte 0 description on page 186 31. updated table 101: option byte 1 description on page 186 32. added table 102: package selection (opt7) on page 187 33. section 15.1.2: external interrupt missed on page 194 : added section on ?external interrupt missed? bug obsolete product(s) - obsolete product(s) st7232axx-auto introduction 17/201 34. section 15.1.6: timd set simultaneously with oc interrupt on page 197 : ? added section concerning limitation of the 16-bit timer ? added ?tbcr1?, ?tbcsr i? and ?tbcsr &? to the workaround subsection 1.2.2 minor content differences 1. removed all references to the sdip32 and sdip42 packages (which are unavailable in automotive) thoughout document 2. replaced tqfp by lqfp throughout document 3. table 3: hardware register map on page 25 : replaced ?h? with ?b? in the reset status column for the scicr1 register 4. system integrity control/status register (sicsr) on page 41 : replaced ?h? with ?b? in the reset value cell of the sicsr register 5. table 43: spi register map and reset values on page 117 : changed the name of bit 5 in the spicsr register from or to ovr 6. break character on page 123 : spi replaced by sci 7. control register 1 (scicr1) on page 133 : replaced ?h? with ?b? in the reset value cell of the scicr1 register 8. changed i l to i lkg in table 77: external clock source on page 161 , figure 65: typical application with an external clock source on page 161 and table 90: iccsel/vpp pin characteristics on page 174 9. table 95: 32-pin lqfp mechanical data on page 182 and table 96: 44-pin lqfp mechanical data on page 183 : altered ?inches? data to four decimal places 10. section 13.3: soldering information on page 184 : ? updated environmental information regarding ?ecopack?? packages ? replaced ecopack tm with ecopack? throughout the document ? updated section on ecopac k? soldering compatability 11. table 98: soldering compatibility (wave and reflow soldering process) on page 184 : removed footnote on pb package maximum temperature 12. updated table 103: flash user programmable device types on page 187 13. added figure 88: flash commercial product code structure on page 188 14. updated section 14.3: rom device ordering information and transfer of customer code on page 188 15. added table 104: fastrom factory coded device types on page 189 16. added figure 89: fastrom commercial product code structure on page 189 17. added table 105: rom factory coded device types on page 190 18. updated figure 90: rom commercial product code structure on page 190 19. updated st72p32a/st7232a (3.8 to 5.5v) microcontroller option list on page 191 20. updated table 106: stmicroelectronics development tools on page 193 21. section 14.4: development tools on page 192 : ? updated introduction and programming tools ? deleted emulators and in-circuit debugging kit ? added evaluation tools and starter kits and development and debugging tools 22. section 14.5: st7 application notes on page 193 : removed list of st7 application notes obsolete product(s) - obsolete product(s) introduction st7232axx-auto 18/201 1.2.3 editing and formatting differences 1. reformatted document 2. converted register and bit decriptions to table format 3. edited english throughout document 4. correctly aligned footnotes of tables throughout document obsolete product(s) - obsolete product(s) st7232axx-auto pin description 19/201 2 pin description figure 2. 32-pin lqfp 7x7 package pinout 1. legend: (hs) = 20ma high sink capability; ei x = associated external interrupt vector iccdata/miso/pc4 ain14/mosi/pc5 iccclk/sck/pc6 ain15/ss /pc7 (hs) pa3 ain13/ocmp1_b/pc1 icap2_b/(hs) pc2 icap1_b/(hs) pc3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10111213141516 1 2 3 4 5 6 7 8 ei1 ei3 ei0 ocmp1_a/ain10/pf4 icap1_a/(hs) pf6 extclk_a/(hs) pf7 ain12/ocmp2_b/pc0 v aref v ssa mco/ain8/pf0 beep/(hs) pf1 v pp /iccsel pa 7 ( h s ) pa 6 ( h s ) pa 4 ( h s ) osc1 osc2 v ss _2 reset pb0 pe1/rdi pe0/tdo v dd _2 pd1/ain1 pd0/ain0 pb4 (hs) pb3 ei2 obsolete product(s) - obsolete product(s) pin description st7232axx-auto 20/201 figure 3. 44-pin lqfp package pinout 1. legend: (hs) = 20ma high sink capability; eix = associated external interrupt vector for external pin connection guidelines, refer to section 12: electrical characteristics on page 153 . in table 2: device pin description below, refer to section 9: i/o ports on page 62 for more details on the software configurat ion of the i/o ports. the reset configuration of each pin is shown in bold. this configuration is valid as long as the device is in reset state. for external pin connection guidelines refer to section 12: electrical characteristics on page 153 . mco/ain8/pf0 beep/(hs) pf1 (hs) pf2 ocmp1_a/ain10/pf4 icap1_a/(hs) pf6 extclk_a/(hs) pf7 v dd_0 v ss_0 ain5/pd5 v aref v ssa 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 ei2 ei3 ei0 ei1 pb3 (hs) pb4 ain0/pd0 ain1/pd1 ain2/pd2 ain3/pd3 ain4/pd4 rdi/pe1 pb0 pb1 pb2 pc6/sck/iccclk pc5/mosi/ain14 pc4/miso/iccdata pc3 (hs)/icap1_b pc2 (hs)/icap2_b pc1/ocmp1_b/ain13 pc0/ocmp2_b/ain12 v ss_1 v dd_1 pa 3 ( h s ) pc7/ss /ain15 v ss _2 reset pa 6 ( h s ) pa 5 ( h s ) pa 4 ( h s ) pe0/tdo v dd _2 osc1 osc2 pa 7 ( h s ) v pp /iccsel obsolete product(s) - obsolete product(s) st7232axx-auto pin description 21/201 table 2. device pin description (1) pin no. pin name type level port main function (after reset) alternate function lqfp44 lqfp32 input output input output float wpu int (2) ana od (3) pp 630pb4 (hs) i/oc t hs x ei3 x x port b4 7 31 pd0/ain0 i/o c t x x x x x port d0 adc analog input 0 8 32 pd1/ain1 i/o c t x x x x x port d1 adc analog input 1 9 - (4) pd2/ain2 i/o c t x x x x x port d2 adc analog input 2 10 - (4) pd3/ain3 i/o c t x x x x x port d3 adc analog input 3 11 - (4) pd4/ain4 i/o c t x x x x x port d4 adc analog input 4 12 - (4) pd5/ain5 i/o c t x x x x x port d5 adc analog input 5 13 1 v aref (5) s analog reference voltage for adc 14 2 v ssa (5) s analog ground voltage 15 3 pf0/mco/ain8 i/o c t xei1xxxport f0 main clock out (f cpu ) adc analog input 8 16 4 pf1 (hs)/beep i/o c t hs x ei1 x x port f1 beep signal output 17 - (4) pf2 (hs) i/o c t hs x ei1 x x port f2 18 5 pf4/ocmp1_a/ ain10 i/o c t xx xx xport f4 timer a output compare 1 adc analog input 10 19 6 pf6 (hs)/icap1_a i/o c t hs x x x x port f6 timer a input capture 1 20 7 pf7 (hs)/extclk_a i/o c t hs x x x x port f7 timer a external clock source 21 - v dd_0 (5) s digital main supply voltage 22 - v ss_0 (5) s digital ground voltage 23 8 pc0/ocmp2_b/ ain12 i/o c t xx xx xport c0 timer b output compare 2 adc analog input 12 24 9 pc1/ocmp1_b/ ain13 i/o c t xx xx xport c1 timer b output compare 1 adc analog input 13 25 10 pc2 (hs)/icap2_b i/o c t hs x x x x port c2 timer b input capture 2 26 11 pc3 (hs)/icap1_b i/o c t hs x x x x port c3 timer b input capture 1 27 12 pc4/miso/ iccdata i/o c t xx x xport c4 spi master in/ slave out data icc data input 28 13 pc5/mosi/ain14 i/o c t xx xx xport c5 spi master out /slave in data adc analog input 14 29 14 pc6/sck/iccclk i/o c t xx x xport c6 spi serial clock icc clock output obsolete product(s) - obsolete product(s) pin description st7232axx-auto 22/201 30 15 pc7/ss /ain15 i/o c t xx xx xport c7 spi slave select (active low) adc analog input 15 31 16 pa3 (hs) i/o c t hs x ei0 x x port a3 32 - v dd_1 (5) s digital main supply voltage 33 - v ss_1 (5) s digital ground voltage 34 17 pa4 (hs) i/o c t hs x x x x port a4 35 - (4) pa 5 ( h s ) i / o c t hs x x x x port a5 36 18 pa6 (hs) i/o c t hs x t port a6 37 19 pa7 (hs) i/o c t hs x t port a7 38 20 v pp /iccsel i must be tied low. in the flash programming mode, this pin acts as the programming voltage input v pp . see section 12.9.2 for more details. high voltage must not be applied to rom devices. 39 21 reset i/o c t top priority non maskable interrupt. 40 22 v ss_2 (5) s digital ground voltage 41 23 osc2 (6) o resonator oscillator inverter output 42 24 osc1 (6) i external clock in put or resonator oscillator inverter input 43 25 v dd_2 (5) s digital main supply voltage 44 26 pe0/tdo i/o c t x x x x port e0 sci transmit data out 127pe1/rdi i/oc t x x x x port e1 sci receive data in 228pb0 i/oc t xei2 xxport b0 caution: negative current injection not allowed on this pin (7) 3- (4) pb1 i/o c t xei2 xxport b1 4- (4) pb2 i/o c t xei2 xxport b2 529pb3 i/oc t xei2 xxport b3 1. legend/abbreviations for table 2 : type: i = input, o = output, s = supply input level: c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration inputs: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ports port and control configuration outputs: od = open drain, pp = push-pull 2. ?eix? defines the associated external inte rrupt vector. if the weak pull-up column (w pu) is merged with the interrupt column (int), then the i/o configuration is pu ll-up interrupt input; otherwise the conf iguration is floating interrupt input table 2. device pin description (1) (continued) pin no. pin name type level port main function (after reset) alternate function lqfp44 lqfp32 input output input output float wpu int (2) ana od (3) pp obsolete product(s) - obsolete product(s) st7232axx-auto pin description 23/201 3. ?t? defines a true open drain i/o (p-buffer and protection diode to v dd are not implemented). see section 9: i/o ports on page 62 and section 12.8: i/o port pin characteristics for more details 4. each i/o port has 8 pads. pads that are not bonded to extern al pins are in input pull-up configuration after reset. the configuration of these pads must be kept at reset state to avoid added current consumption. 5. it is mandatory to connect all available v dd and v aref pins to the supply voltage and all v ss and v ssa pins to ground 6. osc1 and osc2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see section 1: introduction and section 12.5: clock and timing characteristics for more details 7. for details refer to section 12.8.1: general characteristics on page 168 obsolete product(s) - obsolete product(s) register and memory map st7232axx-auto 24/201 3 register and memory map as shown in st7232axx-auto register and memory map 25/201 table 3. hardware register map address block register label register name reset status (1) remarks (2) 0000h 0001h 0002h port a (3) pa d r paddr pao r port a data register port a data direction register port a option register 00h (4) 00h 00h r/w r/w r/w 0003h 0004h 0005h port b (3) pbdr pbddr pbor port b data register port b data direction register port b option register 00h (4) 00h 00h r/w r/w r/w 0006h 0007h 0008h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h (4) 00h 00h r/w r/w r/w 0009h 000ah 000bh port d (3) pdadr pdddr pdor port d data register port d data direction register port d option register 00h (4) 00h 00h r/w r/w r/w 000ch 000dh 000eh port e (3) pedr peddr peor port e data register port e data direction register port e option register 00h (4) 00h 00h r/w r/w (3) r/w (3) 000fh 0010h 0011h port f (3) pfdr pfddr pfor port f data register port f data direction register port f option register 00h (4) 00h 00h r/w r/w r/w 0012h to 0020h reserved area (15 bytes) 0021h 0022h 0023h spi spidr spicr spicsr spi data i/o register spi control register spi control/status register xxh 0xh 00h r/w r/w r/w 0024h 0025h 0026h 0027h itc ispr0 ispr1 ispr2 ispr3 interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 ffh ffh ffh ffh r/w r/w r/w r/w 0028h eicr external interrupt control register 00h r/w 0029h flash fcsr flash control/status register 00h r/w 002ah watchdog wdgcr watchdog control register 7fh r/w 002bh reserved area (1 byte) 002ch 002dh mcc mccsr mccbcr main clock control/status register main clock controller: beep control register 00h 00h r/w r/w 002eh to 0030h reserved area (3 bytes) obsolete product(s) - obsolete product(s) register and memory map st7232axx-auto 26/201 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tac r 2 tac r 1 tac s r ta i c 1 h r taic1lr tao c 1 h r tao c 1 l r tac h r tac l r taachr ta ac l r ta i c 2 h r taic2lr tao c 2 h r tao c 2 l r timer a control register 2 timer a control register 1 timer a control/status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxxx x0xxb xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h reserved area (1 byte) 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbcsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b control/status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxxx x0xxb xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci extended receive prescaler register reserved area sci extended transmit prescaler register c0h xxh 00h x000 0000b 00h 00h 00h read only r/w r/w r/w r/w r/w r/w 0058h to 006fh reserved area (24 bytes) 0070h 0071h 0072h adc adccsr adcdrh adcdrl control/status register data high register data low register 00h 00h 00h r/w read only read only 0073h 007fh reserved area (13 bytes) 1. x = undefined 2. r/w = read/write 3. the bits associated with unavailable pi ns must always keep their reset value 4. the contents of the i/o port dr registers are readable only in output conf iguration. in input confi guration, the values of th e i/o pins are returned instead of the dr register contents table 3. hardware register map (continued) address block register label register name reset status (1) remarks (2) obsolete product(s) - obsolete product(s) st7232axx-auto flas h program memory 27/201 4 flash program memory 4.1 introduction the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte basis using an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features three flash programming modes: ? insertion in a programming tool. in this mode, all sectors including option bytes can be programmed or erased ? icp (in-circuit programming). in this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board ? iap (in-application programming) in this mode, all sectors except sector 0, can be programmed or erased without removing the device from the application board and while the application is running ict (in-circuit testing) for downloading and executing user application test patterns in ram read-out protection register access security sy stem (rass) to prevent accid ental programmin g or erasing 4.3 structure the flash memory is organised in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see ta b l e 4 ). each of these sectors can be erased independently to avoid unnecessary erasing of the whole flas h memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 5 ). they are mapped in the upper part of the st7 addressing space so the reset and interrupt vectors are located in sector 0 (f000h-ffffh). table 4. sectors available in flash devices flash size (bytes) available sectors 4k sector 0 8k sectors 0,1 obsolete product(s) - obsolete product(s) flash program memory st7232axx-auto 28/201 4.3.1 read-out protection read-out protection, when selected, provides a protection against program memory content extraction and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. in flash devices, this protection is removed by reprogramming the option. in this case, the entire program memory is first automatically erased and the device can be reprogrammed. read-out protection selection depends on the device type: in flash devices it is enabled and removed through the fmp_r bit in the option byte in rom devices it is enabled by mask option specified in the option list figure 5. memory map and sector addresses of the st7232x family 4.4 icc interface icc needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see figure 6 ). these pins are: reset : device reset v ss : device power supply ground iccclk: icc output serial clock pin iccdata: icc input/output serial data pin iccsel/v pp : programming voltage osc1(or oscin): main clock input for external source (optional) v dd : application board power supply (optional, see figure 6 , footnote 3) 4 kbytes 4 kbytes 2kbytes sector 1 sector 0 16 kbytes sector 2 8k 16k 32k 60k flash memory size ffffh efffh dfffh 3fffh 7fffh 1000h 24 kbytes 8kbytes 40 kbytes 52 kbytes 9fffh bfffh d7ffh 4k 10k 24k 48k obsolete product(s) - obsolete product(s) st7232axx-auto flas h program memory 29/201 figure 6. typical icc interface 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programmi ng tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not availabl e for the application. if they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. refer to the programming tool docume ntation for recommended resistor values. 2. during the icc session, the programming tool must control the reset pin. this can lead to conflicts between the programming tool and the application reset ci rcuit if it driv es more than 5ma at high level (push pull output or pull-up resistor < 1k). a schott ky diode can be used to isolate the application reset circuit in this case. when using a classical rc netwo rk with r > 1k or a reset management ic with open drain output and pull-up resistor > 1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application dur ing the icc session. 3. the use of pin 7 of the icc connector depends on t he programming tool architecture. this pin must be connected when using most st progr amming tools (it is used to moni tor the application power supply). please refer to the programming tool manual. caution: external clock icc entry mode is mandatory. pin 9 must be connected to the osc1 or oscin pin of the st7 and osc2 must be grounded. 4.5 in-circuit programming (icp) to perform icp the microcontroller must be switched to icc (in-circuit communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the specific microcontroller device, the user needs only to implement the icp hardware interface on the application board (see figure 6 ). for more details on the pin locations, refer to the device pinout description. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (3) 10k ? v ss i ccsel/vpp st7 c l2 c l1 osc1 osc2 application reset source (2) application i/o (1) (see ?caution?) obsolete product(s) - obsolete product(s) flash program memory st7232axx-auto 30/201 4.6 in-application programming (iap) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, ...). for example, it is possible to download code from the spi, sci, usb or can interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.7 related documentation for details on flash programming and icc pr otocol, refer to the st7 flash programming reference manual and to the st7 icc protocol reference manual . flash control/status register (fcsr) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. fcsr reset value: 0000 0000 (00h) 76543210 0 r/w table 5. flash control/status register address and reset value address (hex.)register label76543210 0029h fcsr reset value00000000 obsolete product(s) - obsolete product(s) st7232axx-auto central processing unit 31/201 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 main features enable executing 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) two 8-bit index registers 16-bit stack pointer low power halt and wait modes priority maskable hardware interrupts non-maskable software/hardware interrupts 5.3 cpu registers the 6 cpu registers shown in figure 7 are not present in the memory mapping and are accessed by specific instructions. figure 7. cpu registers 1. x = undefined value accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh obsolete product(s) - obsolete product(s) central processing unit st7232axx-auto 32/201 accumulator (a) the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the following instruction refers to the y register.) the y register is not affected by the interrupt automatic procedures. program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). condition code register (cc) the 8-bit condition code register contains the interrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop instructions. these bits can be individually tested and/or controlled by specific instructions. cc reset value: 111x 1xxx 76543210 1i1hi0nzc r/w r/w r/w r/w r/w r/w r/w obsolete product(s) - obsolete product(s) st7232axx-auto central processing unit 33/201 table 6. cc register description bit bit name function 5,3 i1, i0 interrupt management bits - interrupt the combination of the i1 and i0 bits gives the current interrupt software priority: 10: interrupt software priority = level 0 (main) 01: interrupt software priority = level 1 00: interrupt software priority = level 2 11: interrupt software priority = level 3 (= interrupt disable) these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (ixspr). they can be also set/cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see section 7: interrupts for more details. 4h arithmetic management bit - half carry this bit is set by hardware when a carry occurs between bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred 1: a half carry has occurred this bit is tested using the jrh or jrnh instruction. the h bit is useful in bcd arithmetic subroutines. 2n arithmetic management bit - negative this bit is set and cleared by hardware. it is representative of the result sign of the last arithmetic, logical or data manipulation. it?s a copy of the result 7 th bit. 0: the result of the last operation is positive or null 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1) this bit is accessed by the jrmi and jrpl instructions. 1z arithmetic management bit - zero this bit is set and cleared by hardware. this bit indicates that the result of the last arithmetic, logi cal or data manipulation is zero. 0: the result of the last ope ration is different from zero 1: the result of the last operation is zero this bit is accessed by the jreq and jrne test instructions. 0c arithmetic management bit - carry/borrow this bit is set and cleared by hardware and software. it indicates an overflow or an underflow has occu rred during the last arithmetic operation. 0: no overflow or underflow has occurred 1: an overflow or underflow has occurred this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is al so affected by the ?bit test and branch?, shift and rotate instructions. obsolete product(s) - obsolete product(s) central processing unit st7232axx-auto 34/201 stack pointer register (sp) the stack pointer is a 16-bit register which is always pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 8 ). since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer contains its reset value (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. the previously stored information is then overwritten and therefore lost. the stack also wraps in case of an underflow. the stack is used to save the return address during a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 8 . when an interrupt is received, the sp is decremented and the context is pushed on the stack on return from interrupt, the sp is incremented and the context is popped from the stack a subroutine call occupies two locations and an interrupt five locations in the stack area. sp reset value: 01 ffh 15 14 13 12 11 10 9 8 01 r/w r/w 76543210 sp[7:0] r/w obsolete product(s) - obsolete product(s) st7232axx-auto central processing unit 35/201 figure 8. stack manipulation example 1. legend: stack higher addres = 01ffh; stack lower address = 0100h pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h obsolete product(s) - obsolete product(s) supply, reset and clock management st7232axx-auto 36/201 6 supply, reset and clock management 6.1 introduction the device includes a range of utilit y features for securing the applicat ion in critical situations (for example in case of a power brown-out), and reducing the number of external components. an overview is shown in figure 10 . 6.2 main features optional pll for multiplying the frequency by 2 reset sequence manager (rsm) multi-oscillator clock management (mo) ? 5 crystal/ceramic resonator oscillators 6.3 phase locked loop (pll) if the clock frequency input to the pll is in the range 2 to 4 mhz, the pll can be used to multiply the frequency by two to obtain an f osc2 of 4 to 8 mhz. the pll is enabled by option byte. if the pll is disabled, then f osc2 = f osc /2. caution: the pll is not recommended for applications where timing accuracy is required. caution: when the pll is used with an external clock signal, the clock signal must be available on the oscin pin before the reset signal is released. figure 9. pll block diagram 0 1 pll option bit pll x 2 f osc2 /2 f osc obsolete product(s) - obsolete product(s) st7232axx-auto supply, reset and clock management 37/201 figure 10. clock, reset and supply block diagram 6.4 multi-oscillator (mo) the main clock of the st7 can be generated by two different source types coming from the multi-oscillator block: an external source 4 crystal or ceramic resonator oscillators each oscillator is optimized fo r a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in ta bl e 7 . refer to section 12: electrical characteristics for more details. caution: the osc1 and/or osc2 pins must not be left unconnected. for the purposes of failure mode and effect analysis, it should be noted that if the osc1 and/or osc2 pins are left unconnected, the st7 main oscillator may start a nd, in this configuration, could generate an f osc clock frequency in excess of the allowed maximum (> 16mhz), putting the st7 in an unsafe/undefined state. the product behaviour must therefore be considered undefined when the osc pins are left unconnected. 6.4.1 external clock source in this external clock mode, a clock signal (s quare, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. 6.4.2 crystal/cer amic oscillators this family of oscillators has the advantage of prod ucing a very accurate rate on the main clock of the st7. the selection within a list of 4 oscillators with diff erent frequency ranges has to be done by option byte in order to reduce consumption (refer to section 14.2: flash devices on page 185 for more details on the frequency ranges). in this mode of the multi- oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. the loading capacitance values must be adjust ed according to the selected oscillator. these oscillators are not stopped during the rese t phase to avoid losing time in the oscillator start-up phase. f osc2 multi-oscillator (mo) osc1 reset v ss v dd reset sequence manager (rsm) osc2 main clock controller pll system integrity management watchdog timer sicsr (wdg) with real-time clock (mcc/rtc) wdg rf f osc (option) 0 f cpu 0 0 0 obsolete product(s) - obsolete product(s) supply, reset and clock management st7232axx-auto 38/201 6.5 reset sequence manager (rsm) 6.5.1 introduction the reset sequence manager includes two reset sources as shown in figure 12 : external reset source pulse internal watchdog reset these sources act on the reset pin and it is always kept low during the delay phase. the reset service routine vector is fixed at addresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 11 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (selected by option byte) reset vector fetch caution: when the st7 is unprogrammed or fully erased, the flash is blank and the reset vector is not programmed. for this reason, it is recommended to keep the reset pin in low state until programming mode is entered, in order to avoid unwanted behavior. the 256 or 4096 cpu clock cycle delay allows the oscillator to stab ilise and ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. the reset vector fetch phase duration is 2 clock cycles. table 7. st7 clock source hardware configuration external clock crystal/ceramic resonators osc1 osc2 external source st7 osc1 osc2 load capacitors st7 c l2 c l1 obsolete product(s) - obsolete product(s) st7232axx-auto supply, reset and clock management 39/201 figure 11. reset sequence phases 6.5.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in accordance with the input voltage. it can be pulled low by external circuitry to reset the device. see section 12: electrical characteristics for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 13 ). this detection is asynchronous and therefore the mcu can enter reset state even in halt mode. figure 12. reset block diagram the reset pin is an asynchronous sign al which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 6.5.3 external power on reset to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specified for the selected f osc frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc network connected to the reset pin. reset active phase internal reset 256 or 4096 clock cycles fetch vector reset r on v dd watchdog reset internal reset pulse generator filter obsolete product(s) - obsolete product(s) supply, reset and clock management st7232axx-auto 40/201 6.5.4 internal watchdog reset the reset sequence generated by a internal watchdog counter overflow is shown in figure 13 . starting from the watchdog co unter underflow, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . figure 13. reset sequences reset pin external watchdog t h(rstl)in run watchdog underflow t w(rstl)out run run reset source external reset watchdog reset internal reset (256 or 4096 t cpu ) vector fetch active phase active phase reset obsolete product(s) - obsolete product(s) st7232axx-auto supply, reset and clock management 41/201 6.6 system integrity management system integrity control/status register (sicsr) sicsr reset value: 0000 000x (00b) 76543210 reserved wdgrf -r/w table 8. sicsr register description bit bit name function 7:1 - reserved, must be kept cleared 0 wdgrf watchdog reset flag this bit indicates that the last reset was generated by the watchdog peripheral. it is set by hardware (watchdog reset) and cleared by software (writing zero). obsolete product(s) - obsolete product(s) interrupts st7232axx-auto 42/201 7 interrupts 7.1 introduction the st7 enhanced interrupt management provides the following features: hardware interrupts software interrupt (trap) nested or concurrent interrupt management with flexible interrupt priority and level management: ? up to 4 software programmable nesting levels ? up to 16 interrupt vectors fixed by hardware ? 2 non maskable events: reset, trap this interrupt management is based on: bit 5 and bit 3 of the cpu cc register (i1:0) interrupt software priority registers (isprx) fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order this enhanced in terrupt controller guarant ees full upward compatib ility with the standard (not nested) st7 interrupt controller. 7.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see ta bl e 9 ). the processing flow is shown in figure 14 . when an interrupt request has to be serviced: normal processing is suspended at the end of the current instruction execution the pc, x, a and cc registers are saved onto the stack i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to table 15: interrupt mapping for vector addresses) the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i1 and i0 bits are restored from the stack and the program in the previous level is resumed. obsolete product(s) - obsolete product(s) st7232axx-auto interrupts 43/201 figure 14. interrupt processing flowchart table 9. interrupt software priority levels interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 ?iret? restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw register fetch next reset trap pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt obsolete product(s) - obsolete product(s) interrupts st7232axx-auto 44/201 7.2.1 servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first figure 15 describes this decision process. figure 15. priority decision process when an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. note: 1 the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. 2 reset and trap can be considered as having the highest software priority in the decision process. 7.2.2 different inte rrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, trap) and the maskable type (external or from internal peripherals). pending software different interrupts same highest hardware priority serviced priority highest software priority serviced obsolete product(s) - obsolete product(s) st7232axx-auto interrupts 45/201 7.2.3 non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 14 ). after stacking the pc, x, a and cc registers (except for reset), the corresponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. trap (non maskable software interrupt) this software interrupt is serviced when the tr ap instruction is executed. it is serviced according to the flowchart in figure 14 . reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the highest hardware priority. see section 6.5: reset sequence manager (rsm) . 7.2.4 maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if an y of these two conditions is false, the interrupt is latched and thus remains pending. external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitivity is software selectable through the external interrupt control register (eicr). external interrupt triggered on edge is latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these are logically ored. peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in table 15: interrupt mapping . a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note: the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting to be serviced) is therefore lost if the clear sequence is executed. obsolete product(s) - obsolete product(s) interrupts st7232axx-auto 46/201 7.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column ?exit from halt? in table 15: interrupt mapping ). when several pending interrupts are present while exiting halt mode, the first one serviced can only be an interrupt with exit from halt mode capability and it is selected through the same decision process shown in figure 15 . note: if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 7.4 concurrent and nested management figure 16 and figure 17 show two different interrupt management modes. the first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in figure 17 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0. the software priority is given for each interrupt. warning: a stack overflow may occur without notifying the software of the failure. figure 16. concurrent interrupt management main it4 it2 it1 trap it1 main it0 i1 hardware priority software priority level 3 3 3 3 3 3/0 3 11 11 11 11 11 11/10 11 rim it2 it1 it4 trap it3 it0 it3 i0 10 used stack = 10 bytes obsolete product(s) - obsolete product(s) st7232axx-auto interrupts 47/201 figure 17. nested interrupt management 7.5 interrupt registers cpu cc register interrupt bits main it2 trap main it0 it2 it1 it4 trap it3 it0 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 10 software priority level used stack = 20 bytes hardware priority 11/10 cpu cc reset value: 111x 1010 (xah) 76543210 1i1hi0nzc r/w r/w r/w r/w r/w r/w r/w table 10. cpu cc register description bit bit name function 5, 3 i1, i0 software interrupt priority these two bits indicate the current interrupt software priority: 10: interrupt software priority = level 0 (main) 01: interrupt software priority = level 1 00: interrupt software priority = level 2 11: interrupt software priority = level 3 (= interrupt disable (1) ) these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software priority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop instructions (see table 12: dedicated interrupt instruction set ). 1. trap and reset events can interrupt a level 3 program. obsolete product(s) - obsolete product(s) interrupts st7232axx-auto 48/201 interrupt software priority registers (isprx) these four registers contain the interrupt software priority of each interrupt vector. each interrupt vector (except reset and trap) has corresponding bits in the isprx registers where its own software priority is stored. this correspondance is shown in ta bl e 1 1 . each i1_x and i0_x bit value in the isprx registers has the same meaning as the i1 and i0 bits in the cc register. level 0 can not be written (i1_x = 1, i0_x = 0). in this case, the previously stored value is kept (example, previous = cfh, write = 64h, result = 44h). the reset, and trap vectors have no software priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. caution: if the i1_x and i0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: if the inte rrupt x is still pending (new inte rrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the interrupt x). ispr0 reset value: 1111 1111 (ffh) 76543210 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 r/w r/w r/w r/w r/w r/w r/w r/w ispr1 reset value: 1111 1111 (ffh) 76543210 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 r/w r/w r/w r/w r/w r/w r/w r/w ispr2 reset value: 1111 1111 (ffh) 76543210 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 r/w r/w r/w r/w r/w r/w r/w r/w ispr3 reset value: 1111 1111 (ffh) 76543210 1 1 1 1 i1_13 i0_13 i1_12 i0_12 r r r r r/w r/w r/w r/w table 11. isprx interrupt vector correspondence vector address isprx bits fffbh-fffah i1_0 and i0_0 bits* fff9h-fff8h i1_1 and i0_1 bits -- ffe1h-ffe0h i1_13 and i0_13 bits obsolete product(s) - obsolete product(s) st7232axx-auto interrupts 49/201 7.6 interrupt related instructions 7.7 external interrupts 7.7.1 i/o port in terrupt sensitivity the external interrupt sensitivity is controlled by the ipa, ipb and isxx bits of the eicr register ( figure 18 ). this control allows up to 4 fully independent external interrupt source sensitivities. each external interrupt source can be generated on four (or five) different events on the pin: falling edge rising edge falling and rising edge falling edge and low level rising edge and high level (only for ei0 and ei2) to guarantee correct functionality, the sensitivity bits in the eicr register can be modified only when the i1 and i0 bits of the cc register are both set to 1 (level 3). this means that interrupts must be disabled before changing sensitivity. the pending interrupts are cleared by writing a different value in the isx[1:0], ipa or ipb bits of the eicr. table 12. dedicated interrupt instruction set (1) 1. during the execution of an interrupt routine, t he halt, pop cc, rim, sim and wfi instructions change the current software priority up to the next iret instru ction or one of the previo usly mentioned instructions. instruction new description function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0 = 11 (level 3) i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0 obsolete product(s) - obsolete product(s) interrupts st7232axx-auto 50/201 figure 18. external interrupt control bits is10 is11 eicr pbor.3 pbddr.3 ipb bit pb3 ei2 interrupt source port b [3:0] interrupts pb3 pb2 pb1 pb0 is10 is11 eicr pbor.7 pbddr.7 pb7 ei3 interrupt source port b [7:4] interrupts pb7 pb6 pb5 pb4 is20 is21 eicr sensitivity control paor.3 paddr.3 ipa bit pa 3 ei0 interrupt source port a3 interrupt is20 is21 eicr pfor.2 pfddr.2 pf2 ei1 interrupt source port f [2:0] interrupts pf2 pf1 pf0 sensitivity control sensitivity control sensitivity control obsolete product(s) - obsolete product(s) st7232axx-auto interrupts 51/201 7.8 external interrupt control register (eicr) eicr reset value: 0000 0000 (00h) 76543210 is1[1:0] ipb is2[1:0] ipa reserved r/w r/w r/w r/w - table 13. eicr register description bit bit name function 7:6 is1[1:0] interrupt sensitivity (ei2 and ei3) the interrupt sensitivity, defined usin g the is1[1:0] bits, is applied to the following external interrupts: external interrupt ei2 (port b[3:0]): 00: external interrupt sensitivity = falling edge and low level (ipb bit = 0) and rising edge and high level (ipb bit = 1) 01: external interrupt sensitivity = rising edge only (ipb bit = 0) and falling edge only (ipb bit = 1) 10: external interrupt sensitivit y = falling edge only (ipb bit = 0) and rising edge only (ipb bit = 1) 11: external interrupt sensitivity = rising and falling edge (ipb bit = 0 and 1) external interrupt ei3 (port b[4]): 00: external interrupt sensitivity = falling edge and low level 01: external interrupt sensitivity = rising edge only 10: external interrupt sensitivity = falling edge only 11: external interrupt sensitivity = rising and falling edge these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). 5ipb interrupt polarity for port b this bit is used to invert the sensitivity of the port b [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion obsolete product(s) - obsolete product(s) interrupts st7232axx-auto 52/201 4:3 is2[1:0] interrupt sensitivity (ei0 and ei1) the interrupt sensitivity, defined usin g the is2[1:0] bits, is applied to the following external interrupts: external interrupt ei0 (port a[3:0]): 00: external interrupt sensitivity = falling edge and low level (ipa bit = 0) and rising edge and high level (ipa bit = 1) 01: external interrupt sensitivity = rising edge only (ipa bit = 0) and falling edge only (ipa bit = 1) 10: external interrupt sensitivit y = falling edge only (ipa bit = 0) and rising edge only (ipa bit = 1) 11: external interrupt sensitivity = rising and falling edge (ipa bit = 0 and 1) external interrupt ei1 port ([f2:0]): 00: external interrupt sensitivity = falling edge and low level 01: external interrupt sensitivity = rising edge only 10: external interrupt sensitivity = falling edge only 11: external interrupt sensitivity = rising and falling edge these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). 2ipa interrupt polarity for port a this bit is used to invert the sensitivity of the port a [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion 1:0 - reserved, must always be kept cleared table 13. eicr register description (continued) bit bit name function obsolete product(s) - obsolete product(s) st7232axx-auto interrupts 53/201 7.9 nested interrupts regi ster map and reset value 7.10 interrupt mapping table 14. nested interrupts register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 0024h ispr0 reset value ei1 ei0 mcc + si i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 11 1 0025h ispr1 reset value spi ei3 ei2 i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0026h ispr2 reset value avd sci timer b timer a i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0027h ispr3 reset value 1 1 1 1 i1_13 1 i0_13 1 i1_12 1 i0_12 1 0028h eicr reset value is11 0 is10 0 ipb 0 is21 0 is20 0 ipa 00 0 table 15. interrupt mapping no. source block description register label priority order exit from halt exit from active halt address vector reset reset n/a yes yes fffeh-ffffh trap software interrupt no no fffch-fffdh 0 not used fffah-fffbh 1 mcc/rtc main clock controller time base interrupt mccsr higher priority lower priority yes yes fff8h-fff9h 2 ei0 external interrupt port a[3:0] n/a yes no fff6h-fff7h 3 ei1 external interrupt port f[2:0] yes no fff4h-fff5h 4 ei2 external interrupt port b[3:0] yes no fff2h-fff3h 5 ei3 external interrupt port b[7:4] yes no fff0h-fff1h 6 not used not used ffeeh-ffefh 7 spi spi peripheral interrupts spicsr yes (1) 1. unexpected exit from halt may occur when spi is in slave mode. no ffech-ffedh 8 timer a timer a peripheral interrupts tasr no no ffeah-ffebh 9 timer b timer b peripheral interrupts tbsr no no ffe8h-ffe9h 10 sci sci peripheral interrupts scisr no no ffe6h-ffe7h 11 not used ffe4h-ffe5h obsolete product(s) - obsolete product(s) power saving modes st7232axx-auto 54/201 8 power saving modes 8.1 introduction to give a large measure of flexibility to the ap plication in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 19 ): slow, wait (slow wait), active halt and halt. after a reset the normal operating mode is selected by default (run mode). this mode drives the device (cpu and embedded periphera ls) by means of a master clock which is based on the main osc illator frequency divided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instructi on whose action depends on the oscillator status. figure 19. power saving mode transitions 8.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device to adapt the internal clock frequency (f cpu ) to the available supply voltage slow mode is controlled by three bits in the mccsr register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the master clock frequency (f osc2 ) can be divided by 2, 4, 8 or 16. the cpu and peripherals are clocked at this lower frequency (f cpu ). note: slow wait mode is activated when entering the wait mode while the device is already in slow mode. power consumption wait slow run active halt high low slow wait halt obsolete product(s) - obsolete product(s) st7232axx-auto power saving modes 55/201 figure 20. slow mode clock transitions 8.3 wait mode wait mode places the mcu in a low power consumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i[1:0] bits of the cc register are forced to ?10?, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu remains in wait mode until a reset or an interrupt occurs, causes it to wake up. refer to figure 21 . 00 01 sms cp1:0 f cpu new slow normal run mode request mccsr frequency request f osc2 f osc2 /2 f osc2 /4 f osc2 obsolete product(s) - obsolete product(s) power saving modes st7232axx-auto 56/201 figure 21. wait mode flow-chart 1. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and recovered when the cc register is popped. 8.4 active halt and halt modes active halt and halt modes are the two lowest power consumption modes of the mcu. they are both entered by executing the ?halt? instruction. the decision to enter either in active halt or halt mode is given by the mcc/rtc interrupt enable flag (oie bit in mccsr register). wfi instruction reset interrupt y n n y cpu oscillator peripherals i[1:0] bits on on 10 off fetch reset vector or service interrupt 256 or 4096 cpu clock cycle delay cpu oscillator peripherals i[1:0] bits on off 10 on cpu oscillator peripherals i[1:0] bits on on xx (1) on table 16. active halt and halt power saving modes mccsr oie bit power saving mode entered when halt instruction is executed 0 halt mode 1 active halt mode obsolete product(s) - obsolete product(s) st7232axx-auto power saving modes 57/201 8.4.1 active halt mode active halt mode is the lowest power consumption mode of the mcu with a real-time clock available. it is entered by executing the ?halt? instruction when the oie bit of the main clock controller status regist er (mccsr) is set (see section 10.2: main clock controller with real- time clock and beeper (mcc/rtc) on page 73 for more details on the mccsr register). the mcu can exit active halt mode on reception of either an mcc/rtc interrupt, a specific interrupt (see table 15: interrupt mapping on page 53 ) or a reset. when exiting active halt mode by means of an interrupt, no 256 or 4096 cpu cycle delay occurs. the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 23 ). when entering active halt mode, the i[1:0] bits in the cc register are forced to ?10b? to enable interrupts. therefore, if an interrup t is pending, the mcu wakes up immediately. in active halt mode, only the main oscilla tor and its associated counter (mcc/rtc) are running to keep a wake up time base. all other peripherals are not clocked except those which get their clock supply from another cloc k generator (such as external or auxiliary oscillator). the safeguard against staying locked in active halt mode is provided by the oscillator interrupt. note: as soon as the interrupt capab ility of one of the oscillators is selected (mccsr.oie bit set), entering active halt mode while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. caution: when exiting active halt mode following an interrupt, oie bit of mccsr register must not be cleared before t delay after the interrupt occurs (t delay = 256 or 4096 t cpu delay depending on option byte). otherwise, the st7 enters halt mode for the remaining t delay period. figure 22. active halt timing overview 1. this delay occurs only if the mcu exit s active halt mode by means of a reset halt run run 256 or 4096 cpu cycle delay (1) reset or interrupt halt instruction fetch vector active [mccsr.oie = 1] obsolete product(s) - obsolete product(s) power saving modes st7232axx-auto 58/201 figure 23. active halt mode flow-chart 1. peripheral clocked with an external clock sour ce can still be active 2. only the mcc/rtc interrupt and some specific interru pts can exit the mcu from active halt mode (such as external interrupt). refer to table 15: interrupt mapping on page 53 for more details. 3. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and restored when the cc register is popped. 8.4.2 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the ?halt? instruction when the oie bit of the main clock controller status register (mccsr) is cleared (see section 10.2: main clock controller with real-time clock and beeper (mcc/rtc) on page 73 for more details on the mccsr register). the mcu can exit halt mode on reception of either a specific interrupt (see table 15: interrupt mapping on page 53 ) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is im mediately turned on and the 256 or 4096 cpu cycle delay is used to stabilize the oscillator. after the st art up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 25 ). when entering halt mode, the i[1:0] bits in the cc register are forced to ?10b? to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in halt mode, the main oscillato r is turned off causing all inte rnal processing to be stopped, including the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). halt instruction reset interrupt (2) y n n y fetch reset vector or service interrupt 256 or 4096 cpu clock cycle delay (mccsr.oie = 1) cpu oscillator peripherals (1) i[1:0] bits on off 10 off cpu oscillator peripherals i[1:0] bits on off xx (3) on cpu oscillator peripherals i[1:0] bits on on xx (3) on obsolete product(s) - obsolete product(s) st7232axx-auto power saving modes 59/201 the compatibility of wa tchdog operati on with halt mode is configured by the ?wdghalt? option bit of the option byte. the halt instruction when executed while the watchdog system is enabled, can generate a watchdog reset (see section 14.2 on page 185 ) for more details. figure 24. halt timing overview halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [mccsr.oie = 1] obsolete product(s) - obsolete product(s) power saving modes st7232axx-auto 60/201 figure 25. halt mode flow-chart 1. wdghalt is an option bit. see section 14.2: flash devices for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 15: interrupt mapping on page 53 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and recovered when the cc register is popped. halt instruction reset interrupt (3) y n n y fetch reset vector or service interrupt 256 or 4096 cpu clock watchdog enable disable wdghalt (1) 0 watchdog reset 1 (mccsr.oie = 0) cpu oscillator peripherals (2) i[1:0] bits off off 10 off cpu oscillator peripherals i[1:0] bits on off xx (4) on cycle delay cpu oscillator peripherals i[1:0] bits on on xx (4) on obsolete product(s) - obsolete product(s) st7232axx-auto power saving modes 61/201 halt mode recommendations make sure that an external event is available to wake up the microcontroller from halt mode when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. for the same reason, reinitialize the level sens itiveness of each external interrupt as a precautionary measure. the opcode for the halt instruction is 0 x 8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memory. for example, avoid defining a constant in rom with the value 0x8e. as the halt instruction clears the interrupt ma sk in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake up event (reset or external interrupt). obsolete product(s) - obsolete product(s) i/o ports st7232axx-auto 62/201 9 i/o ports 9.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs for specific pins they offer different functional modes: external interrupt generation alternate signal input/output for the on-chip peripherals an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 functional description each port has 2 main registers: data register (dr) data direction register (ddr) each port also has one optional register: option register (or) each i/o pin may be programmed using the corresponding register bits in the ddr and or registers: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not provide this register refer to section 9.3: i/o port implementation on page 66 ). the generic i/o block diagram is shown in figure 26 . 9.2.1 input modes the input configuration is selected by cleari ng the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. note: 1 writing the dr register modifies the latch value but does not affect the pin status. 2 when switching from input to output mode, the dr register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3 do not use read/modify/write instructions (bset or bres) to modify the dr register as this might corrupt the dr content for i/os configured as input." obsolete product(s) - obsolete product(s) st7232axx-auto i/o ports 63/201 external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external interrupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the eicr register. each external interrupt vector is linked to a dedicated group of i/o port pins (see section 2: pin description and section 7: interrupts ). if several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the eicr register and then logically ored. the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the eicr register must be modified. 9.2.2 output modes the output conf iguration is selected by setting the co rresponding ddr regist er bit. in this case, writing the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. see ta bl e 1 7 for the dr register value and output pin status. 9.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digi tally readable by addressing the dr register. note: input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. table 17. dr register value and output pin status dr push-pull open-drain 0v ss vss 1v dd floating obsolete product(s) - obsolete product(s) i/o ports st7232axx-auto 64/201 figure 26. i/o port general block diagram dr ddr or pad v dd alternate 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) external interrupt source (ei x ) cmos schmitt trigger register access output alternate enable data bus table 18. i/o port mode options configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off (1) off (1) on (2) on (2) pull-up with/without interrupt on (2) output push-pull off (1) on (2) open drain (logic level) off (1) true open drain ni (3) ni (3) ni (4) 1. implemented not activated 2. implemented and activated 3. not implemented 4. the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the device against positive stress. obsolete product(s) - obsolete product(s) st7232axx-auto i/o ports 65/201 caution: the alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. table 19. i/o port configurations hardware configuration input (1) open-drain output (2) push-pull output (2) 1. when the i/o port is in input configuration and the associat ed alternate function is enabled as an output, reading the dr register reads the alternate function output status. 2. when the i/o port is in output configuration and the asso ciated alternate function is enabl ed as an input, the alternate function reads the pin status given by the dr register content. pad v dd r pu external interrupt source (ei x ) data bus pull-up condition interrupt condition dr register access w r dr register alternate input not implemented in true open drain i/o ports analog input pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports pad r pu dr r/w v dd register not implemented in true open drain i/o ports dr register access alternate enable alternate output data bus obsolete product(s) - obsolete product(s) i/o ports st7232axx-auto 66/201 analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected analog pin. warning: the analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 i/o port implementation the hardware implementation on each i/o port depends on the settings in the ddr and or registers and specific feature of the i/o port such as adc input or true open drain. switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommend ed safe transitions are illustrated in figure 27 other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. the i/o port register configurations are summarized in ta b l e 2 0 below. figure 27. interrupt i/o port state transitions 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx =ddr, or obsolete product(s) - obsolete product(s) st7232axx-auto i/o ports 67/201 9.4 low power modes 9.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). table 20. port register configurations port pin name input (ddr = 0) output (ddr = 1) or=0 or=1 or=0 or=1 port a pa[7:6] floating true open-drain pa[5:4] floating pull-up open drain push-pull pa [ 3 ] floating interrupt port b pb[3] pb[4] pb[2:0] pull-up interrupt port c pc[7:0] pull-up port d pd[5:0] port e pe[1:0] port f pf[7:6] pf[4] pf[2] floating interrupt pf[1:0] pull-up interrupt table 21. effect of low power modes on i/o ports mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. table 22. i/o interrupt control/wake-up capability interrupt event event flag enable contro l bit exit from wait exit from halt external interrupt on selected external event - ddrx orx ye s obsolete product(s) - obsolete product(s) i/o ports st7232axx-auto 68/201 table 23. i/o port register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 reset value of all i/o port registers 0 0 0 0 0 0 0 0 0000h padr msb lsb 0001h paddr 0002h paor 0003h pbdr msb lsb 0004h pbddr 0005h pbor 0006h pcdr msb lsb 0007h pcddr 0008h pcor 0009h pddr msb lsb 000ah pdddr 000bh pdor 000ch pedr msb lsb 000dh peddr 000eh peor 000fh pfdr msb lsb 0010h pfddr 0011h pfor obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 69/201 10 on-chip peripherals 10.1 watchdog timer (wdg) 10.1.1 introduction the watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen lo gical conditions, which causes the application program to abandon its normal sequence. the watchdog circuit generates an mcu reset on expiry of a programmed time period, unless the program refreshes the counter?s contents before the t6 bit becomes cleared. 10.1.2 main features programmable free-running downcounter programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte 10.1.3 functional description the counter value stored in the watchdog control register (wdgcr bits t[6:0]), is decremented every 16384 f osc2 cycles (approx.), and the lengt h of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 become s cleared), it initiates a rese t cycle pulling the reset pin low for typically 30s. the application program must write in the wd gcr register at regular intervals during normal operation to prevent an mcu reset. this downcounter is free-running: it counts down even if the watchdog is disabled. the value to be stored in the wdgcr register must be between ffh and c0h: the wdga bit is set (watchdog enabled) the t6 bit is set to prevent generating an immediate reset the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see figure 29: approximate timeout duration ). the timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the wdgcr register (see figure 30 ). following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction generates a reset. obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 70/201 figure 28. watchdog block diagram 10.1.4 how to program the watchdog timeout figure 29 shows the linear relationship between the 6-bit value to be loaded in the watchdog counter (cnt) and the resulting timeout durati on in milliseconds. this can be used for a quick calculation without taking the timing variat ions into account. if more precision is needed, use the formulae in figure 30 . caution: when writing to the wdgcr register, always write 1 in the t6 bit to avoid generating an immediate reset. figure 29. approximate timeout duration reset wdga 6-bit downcounter (cnt) f osc2 t6 t0 wdg prescaler div 4 watchdog control register (wdgcr) t1 t2 t3 t4 t5 msb lsb div 64 0 5 6 11 mcc/rtc tb[1:0] bits (mccsr register) rtc counter 12-bit mcc cnt value (hex.) watchdog timeout (ms) @ 8 mhz. f osc2 3f 00 38 128 1.5 65 30 28 20 18 10 08 50 34 18 82 98 114 obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 71/201 figure 30. exact timeout duration (t min and t max ) where : t min0 = (lsb + 128) x 64 x t osc2 t max0 = 16384 x t osc2 t osc2 = 125ns if f osc2 =8 mhz cnt = value of t[5:0] bits in the wdgcr register (6 bits) msb and lsb are values from the table below depending on the ti mebase selected by the tb[1:0] bits in the mccsr register. to calculate the minimum watchdog timeout (t min ): if then else to calculate the maximum watchdog timeout (t max ): if then else note: in the above formulae, division results must be rounded down to the next integer value. example : with 2ms timeout selected in mccsr register tb1 bit (mccsr reg.) tb0 bit (mccsr reg.) selected mccsr timebase msb lsb 0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54 value of t[5:0] bits in wdgcr register (hex.) min. watchdog timeout (ms) t min max. watchdog timeout (ms) t max 00 1.496 2.048 3f 128 128.552 cnt msb 4 ------------- < t min t min0 16384 cnt t osc2 + = t min t min0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = cnt msb 4 ------------- t max t max0 16384 cnt t osc2 + = t max t max0 16384 cnt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 72/201 10.1.5 low power modes 10.1.6 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the wdgcr is not used. refer to section 14.2: flash devices . 10.1.7 using halt mode with the wdg (wdghalt option) the following recommendation applies if halt mode is used when the watchdog is enabled: before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcontroller. 10.1.8 interrupts none table 24. effect of low power modes on watchdog timer mode description slow no effect on watchdog. wait no effect on watchdog. halt oie bit in mccsr register wdghalt bit in option byte 00 no watchdog reset is generated. the mcu enters halt mode. the watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the mcu receives an external interrupt or a reset. if an external interrupt is received, the watchdog restarts counting after 256 or 4096 cpu clocks. if a reset is generated, the watchdog is disabled (reset state) unless hardware watchdog is selected by option byte. for application recommendations see section 10.1.7 below. 0 1 a reset is generated 1x no reset is generated. the mcu enters active halt mode. the watchdog counter is not decrem ented. it stops counting. when the mcu receives an oscillator interrupt or external interrupt, the watchdog restarts counting immediately. when the mcu receives a reset the watchdog restarts counting after 256 or 4096 cpu clocks. obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 73/201 10.1.9 control register (wdgcr) 10.1.10 watchdog timer regi ster map and reset values 10.2 main clock controller with real-time clock and beeper (mcc/rtc) the main clock controller consists of three different functions: a programmable cpu clock prescaler a clock-out signal to supply external devices a real-time clock timer with interrupt capability each function can be used independently and simultaneously. 10.2.1 programmable cpu clock prescaler the programmable cpu clock prescaler supplies the clock for the st7 cpu and its internal peripherals. it manages slow power saving mode (see section 8.2: slow mode for more details). the prescaler selects the f cpu main clock frequency and is controlled by three bits in the mccsr register: cp[1:0] and sms. wdgcr reset value: 0111 1111 (7fh) 76543210 wdga t[6:0] r/w r/w table 25. wdgcr register description bit bit name function 7wdga activation bit (1) this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled 1. the wdga bit is not used if the hardw are watchdog option is enabled by option byte. 6:0 t[6:0] 7-bit counter (msb to lsb) these bits contain the value of the watchdog counter. they are decremented every 16384 f osc2 cycles (approx.). a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). table 26. watchdog timer register map and reset values address(hex.)register label7 6543210 002ah wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 74/201 10.2.2 clock-out capability the clock-out capability is an alternate function of an i/o port pin that outputs a f osc2 clock to drive external devices. it is controlled by the mco bit in the mccsr register. caution: when selected, the clock out pin suspends the clock during active halt mode. 10.2.3 real-time clock timer (rtc) the counter of the real-time clock timer allows an interrupt to be generated based on an accurate real-time clock. four different time bases depending directly on f osc2 are available. the whole functionality is controlled by four bits of the mccsr register: tb[1:0], oie and oif. when the rtc interrupt is enabled (oie bit set), the st7 enters active halt mode when the halt instruction is executed. see section 8.4: active halt and halt modes for more details. 10.2.4 beeper the beep function is controlled by the mccbcr register. it can output three selectable frequencies on the beep pin (i/o port alternate function). figure 31. main clock controller (mcc/rtc) block diagram div 2, 4, 8, 16 mcc/rtc interrupt sms cp1 cp0 tb1 tb0 oie oif cpu clock mccsr 12-bit mcc rtc counter to cpu and peripherals f osc2 f cpu mco mco bc1 bc0 mccbcr beep selection beep signal 1 0 to watchdog timer div 64 obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 75/201 10.2.5 low power modes 10.2.6 interrupts the mcc/rtc interrupt event generates an interrupt if the oie bit of the mccsr register is set and the interrupt mask in the cc register is not active (rim instruction). table 27. effect of low power modes on mcc/rtc mode description wait no effect on mcc/rtc peripheral mcc/rtc interrupt causes the de vice to exit from wait mode active halt no effect on mcc/rtc counter (oie bit is set), the registers are frozen mcc/rtc interrupt causes the device to exit from active halt mode halt mcc/rtc counter and registers are frozen mcc/rtc operation resumes when the mcu is woken up by an interrupt with ?exit from halt? capability table 28. mcc/rtc interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt time base overflow event oif oie yes no (1) 1. the mcc/rtc interrupt wakes up the mcu from active halt mode, not from halt mode. obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 76/201 10.2.7 mcc/rtc registers mcc control/status register (mccsr) mccsr reset value: 0000 0000 (00h) 76543210 mco cp[1:0] sms tb[1:0] oie oif r/w r/w r/w r/w r/w r/w table 29. mccsr register description bit bit name function 7mco main clock out selection this bit enables the mco alternate function on the pf0 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f cpu on i/o port) note: to reduce power consumption, the mco function is not active in active halt mode. 6:5 cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software. 00: f cpu in slow mode = f osc2 /2 01: f cpu in slow mode = f osc2 /4 10: f cpu in slow mode = f osc2 /8 11: f cpu in slow mode = f osc2 /16 4sms slow mode select this bit is set and cleared by software. 0: normal mode, f cpu =f osc2 1: slow mode, f cpu is given by cp1, cp0; see section 8.2: slow mode and section 10.2: main clock co ntroller with real-time clock and beeper (mcc/rtc) for more details. 3:2 tb[1:0] time base control these bits select the programmable divider time base. they are set and cleared by software: 00: time base (for counter prescaler 16000) = 4ms (f osc2 =4mhz) and 2ms (f osc2 =8mhz) 01: time base (for counter prescaler 32000) = 8ms (f osc2 =4mhz) and 4ms (f osc2 =8mhz) 10: time base (for counter prescaler 80000) = 20ms (f osc2 =4mhz) and 10ms (f osc2 =8mhz) 11: time base (for counter prescaler 200000) = 50ms (f osc2 = 4mhz) and 25ms (f osc2 =8mhz) a modification of the time base is taken into account at the end of the current period (previou sly set) to avoid an unwanted time shift. this allows use of this time base as a real-time clock. obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 77/201 mcc beep control register (mccbcr) 1oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt can be used to exit from active halt mode. when this bit is set, calling the st7 software halt instruction enters the active halt power saving mode . 0oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the mccsr register. it indicates when set that the main oscillator has reached the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached caution: the bres and bset instructions must not be used on the mccsr register to avoid unintentionally clearing the oif bit. mccbcr reset value: 0000 0000 (00h) 76543210 reserved bc[1:0] -r/w table 30. mccbcr register description bit bit name function 7:2 - reserved, must be kept cleared 1:0 bc[1:0] beep control these 2 bits select the pf1 pin beep capability: 00: beep mode (with f osc2 =8mhz)=off 01: beep mode (with f osc2 = 8mhz) = ~2-khz (output beep signal ~ 50% duty cycle) 10: beep mode (with f osc2 = 8mhz) = ~1-khz (output beep signal ~ 50% duty cycle) 11: beep mode (with f osc2 = 8mhz) = ~500-hz (output beep signal ~ 50% duty cycle) the beep output signal is available in active halt mode but has to be disabled to reduce the consumption. table 29. mccsr register description (continued) bit bit name function obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 78/201 10.2.8 mcc register map and reset values 10.3 16-bit timer 10.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input signals ( input capture ) or generation of up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequencies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 10.3.2 main features programmable prescaler: f cpu divided by 2, 4 or 8 overflow status flag and maskable interrupt external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge 1 or 2 output compare functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt 1 or 2 input capture functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm one pulse mode table 31. main clock controller register map and reset values address(hex.) register label 7 6 5 4 3 2 1 0 002ch mccsr reset value mco 0 cp1 0 cp0 0 sms 0 tb1 0 tb0 0 oie 0 oif 0 002dh mccbcr reset value 0 0 0 0 0 0 bc1 0 bc0 0 obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 79/201 reduced power mode 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk) (a) the block diagram is shown in figure 32 . 10.3.3 functional description counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high and low. counter register (cr) counter high register (chr) is the most significant byte (ms byte) counter low register (clr) is the least significant byte (ls byte) alternate counter register (acr) alternate counter high register (achr) is the most significant byte (ms byte) alternate counter low register (aclr) is the least significant byte (ls byte) these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see 16-bit read sequence (from either the counter register or alternate counter register) on page 81 ). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit timer). the reset value of both counte rs is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits (bits 3 and 2) of the cr2 register, as illustrated in table 36: cr2 register description . the value in the counter register repeats every 131072, 262144 or 524288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. caution: in flash devices, timer a functionality has the following restrictions: taoc2hr and taoc2lr registers are write only input capture 2 is not implemented the corresponding interrupts cannot be used (icf2, ocf2 forced by hardware to zero) a. some timer pins may not be avai lable (not bonded) in some st7 dev ices. refer to the device pinout description. when reading an input signal on a non-bonded pin, the value is always ?1?. obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 80/201 figure 32. timer block diagram 1. if ic, oc and to interrupt requests have separate vectors then the last or is not present (see table 15: interrupt mapping on page 53 ). mcu-peripheral interface alternate counter output compare register output compare circuit edge detect circuit 1 overflow detect circuit 1/2 1/4 1/8 8-bit buffer latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 cr1 (control register 1) cr2 (control register 2) csr (control/status register) 6 16 8 8 8 8 8 8 exedg timer internal bus edge detect circuit 2 1 cc[1:0] counter register pin pin register (1) st7 internal bus high low high low high low high low output compare register 2 input capture register 1 input capture register 2 pin pin pin obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 81/201 16-bit read sequence (from either the counter register or alternate counter register) figure 33. 16-bit read sequence the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they return the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, output compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set a timer interrupt is generated if the toie bit of the cr1 register is set and the i bit of the cc register is cleared if one of these conditions is false, the interr upt remains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set 2. an access (read or write) to the clr register note: the tof bit is not cleared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). read ms byte at t0 returns buffered ls byte value at t0 at t0 + ? t other beginning of the sequence sequence completed ls byte is buffered instructions read ls byte obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 82/201 external clock the external clock (where available) is selected if cc0 = 1 and cc1 = 1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the external clock pin extclk that triggers the free running counter. the counter is synchronize d with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur betw een two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the cpu clock frequency. figure 34. counter timing diagram, internal clock divided by 2 figure 35. counter timing diagram, internal clock divided by 4 figure 36. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high, when it is low the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 83/201 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two 16-bit input capture registers (ic1r and ic2r) are used to latch the value of the free running counter after a transition is detected on the icap i pin (see below). ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure to use the input capture function select the following in the cr2 register: the timer clock (cc[1:0]) (see table 36: cr2 register description ) the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input or in put with pull-up without interrupt if this configuration is available). select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin. select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). when an input capture occurs: icf i bit is set the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 38 ). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. otherwise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. by reading the sr register while the icf i bit is set 2. by accessing (reading or writing) the ic i lr register msb lsb icir ic i hr ic i lr obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 84/201 note: 1 after reading the icihr regist er, transfer of input capture data is inhibited and icfi is never set until the icilr register is also read. 2 the icir register contains the free running counter value which corresponds to the most recent input capture. 3 the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4 in one pulse mode and pwm mode only input capture 2 can be used. 5 the alternate inputs (icap1 and icap2) are always directly connected to the timer. so any transitions on these pins activates the input capture function. moreover if one of the icapi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the icie bit is set. this can be avoided if the input capture f unction i is disabled by reading the icihr (see note 1). 6 the tof bit can be used with interrupt generation in order to measure events that go beyond the timer range (ffffh). 7 in flash devices, the icap2 registers (taic2hr, taic2lr) are not available on timer a. the corresponding interrupts cannot be used (icf2 is forced by hardware to 0). figure 37. input capture block diagram icie cc0 cc1 iedg1 cr1 (control register 1) cr2 (control register 2) icf2 icf1 0 0 0 sr (status register) iedg2 icap1 icap2 ic1r register pin pin edge detect circuit 2 edge detect circuit 1 ic2r register 16-bit free running counter 16-bit obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 85/201 figure 38. input capture timing diagram 1. the rising edge is the active edge. output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output compare register and the free running counter, the output compare function: assigns pins with a programmable value if the oc i e bit is set sets a flag in the status register generates an interrupt if enabled two 16-bit registers, output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle (see below). these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure to use the output compare function, select the following in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. select the timer clock (cc[1:0]) (see table 36: cr2 register description ) select the following in the cr1 register: select the olvl i bit to applied to the ocmp i pins after the match occurs set the ocie bit to generate an interrupt if it is needed msb lsb oc i roc i hr oc i lr ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 86/201 when a match is found between ocri register and cr register: ocf i bit is set the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset) a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific timing application can be calculated using the following formula: where: if the timer clock is an external clock, the formula is: where: clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set 2. accessing (reading or writing) the oc i lr register the following procedure is recommended to prevent the ocf i bit from being set between the time it is read and the write to the oc i r register: write to the oc i hr register (further compares are inhibited) read the sr register (first step of the clearance of the ocf i bit, which may be already set) write to the oc i lr register (enables the output compare function and clears the ocf i bit) ? t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see table 36: cr2 register description ) ? t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) ? oc i r= ? t * f cpu presc ? oc i r= ? t * f ext obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 87/201 note: 1 after a processor write cycle to the ocihr r egister, the output compar e function is inhibited until the ocilr register is also written. 2 if the ocie bit is not set, the ocmpi pin is a general i/o port and the olvli bit does not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3 in both internal and external clock modes, ocfi and ocmpi are set while the counter value equals the ocir register value (see figure 40 on page 88 for an example with f cpu /2 and figure 41 on page 88 for an example with f cpu /4). this behavior is the same in opm or pwm mode. 4 the output compare functions can be used both for generating external events on the ocmpi pins even if the input capture mode is also used. 5 the value in the 16-bit oc i r register and the olvi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. 6 in flash devices, the taoc2hr, taoc2lr registers are ?write only? in timer a. the corresponding event cannot be generated (ocf2 is forced by hardware to 0). forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit = 1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. the folvl i bits have no effect in both one pulse mode and pwm mode. figure 39. output compare block diagram 16-bit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie cr1 (control register 1) cr2 (control register 2) 0 0 0 ocf2 ocf1 sr (status register) 16-bit ocmp1 ocmp2 latch 1 oc2r register pin pin folv2 folv1 16-bit output compare circuit latch 2 obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 88/201 figure 40. output compare timing diagram, f timer =f cpu /2 figure 41. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocri) output compare flag i (ocfi) ocmpi pin (olvli = 1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocri) ocmpi pin (olvli = 1) output compare flag i (ocfi) obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 89/201 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode: 1. load the oc1r register with the value corresponding to the length of the pulse using the appropriate formula below according to the timer clock source used 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after the pulse ? using the olvl2 bit, select the level to be applied to the ocmp1 pin during the pulse ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input) 3. select the following in the cr2 register: ? set the oc1e bit (the ocmp1 pin is then dedicated to the output compare 1 function) ? set the opm bit ? select the timer clock cc[1:0] (see table 36: cr2 register description ) figure 42. one pulse mode sequence then, on a valid event on the icap1 pin, the counter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set 2. accessing (reading or writing) the ic i lr register ocmp1 = olvl1 when when event occurs on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter counter = ocir obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 90/201 the oc1r register value required for a specif ic timing application can be calculated using the following formula: where: if the timer clock is an external clock the formula is: where: when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 43 ). note: 1 the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3 if olvl1 = olvl2 a continuous signal is seen on the ocmp1 pin. 4 the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5 when one pulse mode is used oc1r is dedic ated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level olvl2 is dedicated to the one pulse mode. 6 in flash devices, timer a ocf2 bit is forced by hardware to 0. t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on the cc[1:0] bits, see table 36: cr2 register description ) t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) oc i r value = t * f cpu presc - 5 oc i r= t * f ext -5 obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 91/201 figure 43. one pulse mode timing example 1. iedg1 = 1, oc1r = 2ed0h, olvl1 = 0, olvl2 = 1 figure 44. pulse width modulation mode timing example with 2 output compare functions 1. oc1r = 2ed0h, oc2r = 34e2, olvl1 = 0, olvl2 = 1 counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 01f8 01f8 2ed3 ic1r counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 fffc fffd fffe 2ed0 2ed1 2ed2 obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 92/201 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r register, and so this functionality can no t be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values written in the oc1r and oc2r registers are taken into account only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). procedure to use pulse width modulation mode: 1. load the oc2r register with the value corresponding to the period of the signal using the appropriate formula below according to the timer clock source used 2. load the oc1r register with the value corresponding to the period of the pulse if (olvl1 = 0 and olvl2 = 1) using the appropriate formula below according to the timer clock source used 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc1r register ? using the olvl2 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc2r register 4. select the following in the cr2 register: ? set oc1e bit (the ocmp1 pin is then dedicated to the output compare 1 function) ? set the pwm bit ? select the timer clock (cc[1:0]) (see table 36: cr2 register description ) figure 45. pulse width modulation cycle if olvl1 = 1 and olvl2 = 0 the length of the positive pulse is the difference between the oc2r and oc1r registers. if olvl1 = olvl2 a continuous signal is seen on the ocmp1 pin. ocmp1 = olvl2 ocmp1 = olvl1 when counter = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set when counter = oc2r obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 93/201 the oc i r register value required for a specific timing application can be calculated using the following formula:: where: if the timer clock is an external clock the formula is: where: the output compare 2 event causes the counter to be initialized to fffch (see figure 44 ) note: 1 after a write instruction to the ocihr register, the output co mpare function is inhibited until the ocilr register is also written. 2 the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 3 the icf1 bit is set by hardware when the c ounter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4 in pwm mode the icap1 pin can not be used to perform input capture because it is disconnected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 5 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see ta b l e 3 6 ) t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) oc i r value = t * f cpu presc - 5 oc i r= t * f ext -5 obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 94/201 10.3.4 low power modes 10.3.5 interrupts table 32. effect of low power modes on 16-bit timer mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with ?exit from halt mode? capability or from the counter reset va lue when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequently, when the mcu is woken up by an interrupt with ?exit from halt mode? capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. table 33. 16-bit timer interrupt control/wake-up capability (1) 1. the 16-bit timer interrupt events are connec ted to the same interrupt vector (see section 7: interrupts ). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). interrupt event event flag en able control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie ye s n o input capture 2 event icf2 output compare 1 event (not available in pwm mode) ocf1 ocie output compare 2 event (not available in pwm mode) ocf2 timer overflow event tof toie obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 95/201 10.3.6 summary of timer modes 10.3.7 16-bit timer registers each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. control register 1 (cr1) table 34. summary of timer modes modes timer resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1) and/or (2) 1. see note 4 in one pulse mode on page 89 2. see note 5 and 6 in one pulse mode on page 89 ye s ye s (2) ye s ye s output compare (1) and/or (2) ye s one pulse mode no not recommended (1) no partially (2) pwm mode not recommended (3) 3. see note 4 in pulse width modulation mode on page 92 no cr1 reset value: 0000 0000 (00h) 76543210 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 r/w r/w r/w r/w r/w r/w r/w r/w table 35. cr1 register description bit bit name function 7icie input capture interrupt enable 0: interrupt is inhibited 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set 6ocie output compare interrupt enable 0: interrupt is inhibited 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set 5 toie timer overflow interrupt enable 0: interrupt is inhibited 1: a timer interrupt is enabled whenever the tof bit of the sr register is set obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 96/201 4folv2 forced output compare 2 this bit is set and cleared by software. 0: no effect on the ocmp2 pin 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison 3folv1 forced output compare 1 this bit is set and cleared by software. 0: no effect on the ocmp1 pin 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no successful comparison 2olvl2 output level 2 this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r register and ocxe is set in the cr2 register. this value is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. 1iedg1 input edge 1 this bit determines which type of level transition on the icap1 pin triggers the capture. 0: a falling edge triggers the capture 1: a rising edge triggers the capture 0olvl1 output level 1 the olvl1 bit is copied to the ocmp1 pin whenever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. table 35. cr1 register description (continued) bit bit name function obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 97/201 control register 2 (cr2) cr2 reset value: 0000 0000 (00h) 76543210 oc1e oc2e opm pwm cc[1:0] iedg2 exedg r/w r/w r/w r/w r/w r/w r/w table 36. cr2 register description bit bit name function 7ocie output compare 1 pin enable this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output compare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o) 1: ocmp1 pin alternate function enabled 6oc2e output compare 2 pin enable this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output compare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general- purpose i/o) 1: ocmp2 pin alternate function enabled 5opm one pulse mode 0: one pulse mode is not active 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. 4pwm pulse width modulation 0: pwm mode is not active 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r register. 3:2 cc[1:0] clock control the timer clock mode depends on the following bits: 00: timer clock = f cpu /4 01: timer clock = f cpu /2 10: timer clock = f cpu /8 11: timer clock = external clock (where available) note: if the external clock pin is not available, programming the external clock configur ation stops the counter. obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 98/201 control/status register (csr) 1iedg2 input edge 2 this bit determines which type of level transition on the icap2 pin triggers the capture. 0: a falling edge triggers the capture 1: a rising edge triggers the capture 0 exedg external clock edge this bit determines which type of level transition on the external clock pin extclk triggers the counter register. 0: a falling edge triggers the counter register 1: a rising edge triggers the counter register csr reset value: xxxx x0xx (xxh) 76543210 icf1 ocf1 tof icf2 ocf2 timd reserved rrrrrr/w - table 37. csr register description bit bit name function 7icf1 input capture flag 1 0: no input capture (reset value) 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. 6ocf1 output compare flag 1 0: no match (reset value) 1: the content of the free runnin g counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. 5tof timer overflow flag 0: no timer overflow (reset value) 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr r egister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof 4icf2 input capture flag 2 0: no input capture (reset value) 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register , then read or write the low byte of the ic2r (ic2lr) register. table 36. cr2 register description (continued) bit bit name function obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 99/201 input capture 1 high register (ic1hr) this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). output compare 1 high register (oc1hr) this is an 8-bit register that contains the high part of the value to be compared to the chr register. 3ocf2 output compare flag 2 0: no match (reset value) 1: the content of the free runnin g counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. 2timd timer disable this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disables the output functions (ocmp1 and ocmp2 pins) to reduce power consumption. access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled 1:0 - reserved, must be kept cleared ic1hr reset value: undefined 76543210 msb lsb rrrrrrrr ic1lr reset value: undefined 76543210 msb lsb rrrrrrrr oc1hr reset value: 1000 0000 (80h) 76543210 msb lsb r/w r/w r/w r/w r/w r/w r/w r/w table 37. csr register description (continued) bit bit name function obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 100/201 output compare 1 low register (oc1lr) this is an 8-bit register that contains the low part of the value to be compared to the clr register. output compare 2 high register (oc2hr) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) this is an 8-bit register that contains the high part of the counter value. oc1lr reset value: 0000 0000 (00h) 76543210 msb lsb r/w r/w r/w r/w r/w r/w r/w r/w oc2hr reset value: 1000 0000 (80h) 76543210 msb lsb r/w r/w r/w r/w r/w r/w r/w r/w oc2lr reset value: 0000 0000 (00h) 76543210 msb lsb r/w r/w r/w r/w r/w r/w r/w r/w chr reset value: 1111 1111 (ffh) 76543210 msb lsb rrrrrrrr obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 101/201 counter low register (clr) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. alternate counter high register (achr) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. input capture 2 high register (ic2hr) this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). clr reset value: 1111 1100 (fch) 76543210 msb lsb rrrrrrrr achr reset value: 1111 1111 (ffh) 76543210 msb lsb rrrrrrrr aclr reset value: 1111 1100 (fch) 76543210 msb lsb rrrrrrrr ic2hr reset value: undefined 76543210 msb lsb rrrrrrrr obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 102/201 input capture 2 low register (ic2lr) this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 2 event). 16-bit timer register map and reset values ic2lr reset value: undefined 76543210 msb lsb rrrrrrrr table 38. 16-bit timer register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 csr reset value icf1 x ocf1 x tof x icf2 x ocf2 x timd 0 - x - x timer a: 34 timer b: 44 ic1hr reset value msb xxxxxxx lsb x timer a: 35 timer b: 45 ic1lr reset value msb xxxxxxx lsb x timer a: 36 timer b: 46 oc1hr reset value msb 1000 0 0 0 lsb 0 timer a: 37 timer b: 47 oc1lr reset value msb 0000 0 0 0 lsb 0 timer a: 3e timer b: 4e oc2hr reset value msb 1000 0 0 0 lsb 0 timer a: 3f timer b: 4f oc2lr reset value msb 0000 0 0 0 lsb 0 timer a: 38 timer b: 48 chr reset value msb 1111 1 1 1 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111 1 1 0 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111 1 1 1 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111 1 1 0 lsb 0 timer a: 3c timer b: 4c ic2hr reset value msb xxxxxxx lsb x timer a: 3d timer b: 4d ic2lr reset value msb xxxxxxx lsb x obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 103/201 10.4 serial peripheral interface (spi) 10.4.1 introduction the serial peripheral interface (spi) allows full-duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves however the spi interface can not be a master in a multi-master system. 10.4.2 main features full duplex synchronous transfers (on 3 lines) simplex synchronous transfers (on 2 lines) master or slave operation six master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note below) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag. write collision, master mo de fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 10.4.3 general description figure 46 shows the serial peripheral interface (spi) block diagram. there are 3 registers: spi control register (spicr) spi control/status register (spicsr) spi data register (spidr) the spi is connected to external devices through 4 pins: miso: master in/slave out data mosi: master out / slave in data sck: serial clock out by spi masters and input by spi slaves ss : slave select: this input signal acts as a ?chip select? to let the spi master communicate with slaves individually and to avoid contention on the data lines. slave ss inputs can be driven by standard i/o ports on the master mcu. obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 104/201 figure 46. serial peripheral interface block diagram functional description a basic example of interconnections between a single master and a single slave is illustrated in figure 47 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is always initiated by th e master. when the master device transmits data to a slave device via mosi pin, the sl ave device responds by sending data to the master device via the miso pin. this implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node ( in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 50 ) but master and slave must be programmed with the same timing mode. write spi state control spie spe mstr cpha spr0 spr1 cpol mosi miso ss sck spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0 data/address bus read buffer 8-bit shift register read spidr serial clock generator obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 105/201 figure 47. single master/s ingle slave application slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr register (see figure 49 ) in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 48 ): if cpha = 1 (data latched on 2nd clock edge): ss internal must be held low during the entire transmission. this im plies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by managing the ss function by software (ssm = 1 and ssi = 0 in the in the spicsr register) if cpha = 0 (data latched on 1st clock edge): ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. if ss is not pulled high, a write collision error occurs when the slave writes to the shift register (see write collision error (wcol) on page 110 ). miso mosi mosi miso sck sck ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software spi clock generator 8-bit shift register 8-bit shift register master slave obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 106/201 figure 48. generic ss timing diagram figure 49. hardware/software slave select management master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). to operate the spi in master mode, perform the following steps in order: 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 50 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note: 1 if the spicsr register is not written first, the spicr register setting (mstr bit) may be not taken into account. 2 mstr and spe bits rema in set only if ss is high). the transmit sequence begins when software writes a byte in the spidr register. byte 1 byte 2 byte 3 mosi/miso master ss slave ss if cpha = 0 slave ss if cpha = 1 1 0 ss internal ssm bit ssi bit ss external pin obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 107/201 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the most significant bit of the mosi pin first. when data transfer is complete: the spif bit is set by hardware an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the following actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 50 ) note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in slave select management on page 105 and figure 48 . if cpha = 1 ss must be held low continuously. if cpha = 0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and se t the spe bit to enable the spi i/o functions. slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the most significant bit of the miso pin first. the transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its mosi pin. when data transfer is complete: the spif bit is set by hardware an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a write or a read to the spidr register note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 108/201 the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see overrun condition (ovr) on page 110 ). 10.4.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 50 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 50 , shows an spi transfer with the four combinations of the cpha and cpol bits. the diagram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit. obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 109/201 figure 50. data clock timing diagram 1. this figure should not be used as a replac ement for parametric information. refer to section 12: electrical characteristics . msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) ss (to slave) capture strobe cpha = 0 cpha = 1 (cpol = 1) sck (cpol = 0) sck mos1 (from slave) msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) ss (to slave) capture strobe (cpol = 1) sck (cpol = 0) sck mos1 (from slave) obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 110/201 10.4.5 error flags master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: the modf bit is set and an spi interrupt request is generated if the spie bit is set the spe bit is reset. this blocks all output from the device and disables the spi peripheral. the mstr bit is reset, thus forcing the device into slave mode clearing the modf bit is done through a software sequence: 1. a read access to the spicsr regi ster while the modf bit is set 2. a write to the spicr register note: to avoid any conflicts in an ap plication with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their original state during or after this clearing sequence. hardware does not allow the us er to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. overrun condition (ovr) an overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs, the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. write collision error (wcol) a write collision occurs when the software trie s to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted and the software write is unsuccessful. write collisions can occur both in master and slave mode. see also slave select management on page 105 . note: a?read collision? never occurs since the receiv ed data byte is placed in a buffer in which access is always synchronous with the mcu operation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 51 ). obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 111/201 figure 51. clearing the wcol bit (write collision flag) software sequence 1. writing to the spidr register instead of reading it does not reset the wcol bits. single master systems a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 52 ). the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports are forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master receives the previous byte back from the slave device if all miso and mosi pins are connected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with command fields. clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif = 0 wcol = 0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol = 0 read spicsr read spidr result result obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 112/201 figure 52. single master/mul tiple slave configuration 10.4.6 low power modes using the spi to wakeup the mcu from halt mode in slave configuration, the spi is able to wakeup the st7 device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to perform an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the st7 from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the st7 enters halt mode. so if slave selection is configured as external (see slave select management on page 105 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. miso mosi ss sck 5v por ts master ss sck mosi miso slave mcu ss sck mosi miso slave mcu ss sck mosi miso slave mcu ss sck mosi miso slave mcu mcu table 39. effect of low power modes on spi mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the mcu is woken up by an interrupt with ?exit from halt mode? capability. the data received is subsequently read from the spidr r egister when the software is running (interrupt vector fetching). if several data are received before the wake up event, then an overrun error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device. obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 113/201 10.4.7 interrupts 10.4.8 spi registers control register (spicr) table 40. spi interrupt control/wake-up capability (1) 1. the spi interrupt events are connecte d to the same interrupt vector (see section 7: interrupts ). they generate an interrupt if the correspondi ng enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes ye s master mode fault event modf no overrun error ovr spicr reset value: 0000 xxxx (0xh) 76543210 spie spe spr2 mstr cpol cpha spr[1:0] r/w r/w r/w r/w r/w r/w r/w table 41. spicr register description bit bit name function 7 spie s erial peripheral interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generat ed whenever spif = 1, modf = 1 or ovr = 1 in the spicsr register 6 spe serial peripheral output enable this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see master mode fault (modf) on page 110 ). the spe bit is cleared by re set, so the spi peripheral is not initially connected to the external pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled 5 spr2 divider enable this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate (see bits [1:0] below). 0: divider by 2 enabled 1: divider by 2 disabled note: the spr2 bit has no effect in slave mode obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 114/201 4mstr master mode this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see master mode fault (modf) on page 110 ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are reversed. 3cpol clock polarity this bit is set and cleared by software. this bit determines the idle state of the serial clock. the cp ol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note: if cpol is changed at the communication byte boundaries, the spi must be disabled by resetting the spe bit. 2cpha clock phase this bit is set and cleared by software. 0: the first clock transition is the first data capture edge 1: the second clock transition is the first capture edge note: the slave must have the same cpol and cpha settings as the master. 1:0 spr[1:0] serial clock frequency these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode: 100: serial clock = f cpu /4 000: serial clock = f cpu /8 001: serial clock = f cpu /16 110: serial clock = f cpu /32 010: serial clock = f cpu /64 011: serial clock = f cpu /128 note: these 2 bits have no effect in slave mode. table 41. spicr register description (continued) bit bit name function obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 115/201 control/status register (spicsr) spicsr reset value: 0000 0000 (00h) 76543210 spif wcol ovr modf - sod ssm ssi r r r r r/w r/w r/w r/w table 42. spicsr register description bit bit name function 7 spif serial peripheral data transfer flag this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie = 1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared 1: data transfer between the device and an external device has been completed note: while the spif bit is set, a ll writes to the spidr register are inhibited until the spicsr register is read. 6wcol write collision status this bit is set by hardware when a write to the spidr register is done during a transmit sequence. it is cleared by a software sequence (see figure 51 ). 0: no write collision occurred 1: a write collision has been detected 5ovr spi overrun error this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see overrun condition (ovr) on page 110 ). an interrupt is generated if spie = 1 in spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected 4modf mode fault flag this bit is set by hardware when the ss pin is pulled low in master mode (see master mode fault (modf) on page 110 ). an spi interrupt can be generated if spie = 1 in the spicsr register. this bit is cleared by a software sequence (an access to the spicr register while modf = 1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected 3 - reserved, must be kept cleared. 2sod spi output disable this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode/miso in slave mode). 0: spi output enabled (if spe = 1) 1: spi output disabled obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 116/201 data i/o register (spidr) the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register initiates transmission/reception of another byte. note: 1 during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. 2 while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value located in the buffer and not the content of the shift register (see figure 46 ). 1 ssm ss management this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see slave select management on page 105 . 0: hardware management (ss managed by external pin) 1: software management (internal ss signal controlled by ssi bit. external ss pin free for general-purpose i/o) 0 ssi ss internal mode this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0 : slave selected 1 : slave deselected spidr reset value: undefined 76543210 d[7:0] r/w table 42. spicsr register description (continued) bit bit name function obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 117/201 spi register map and reset values 10.5 serial communicat ions interface (sci) 10.5.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci offers a very wide range of baud rates using two baud rate generator systems. 10.5.2 main features full duplex, asynchronous communications nrz standard format (mark/space) dual baud rate generator systems independently programmable transmit and receive baud rates up to 500k baud programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags two receiver wake up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver four error detection flags: ? overrun error ? noise error ?frame error ? parity error five interrupt sources with flags: ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error detected table 43. spi register map and reset values addres (hex.) register label 7 6 5 4 3 2 1 0 0021h spidr reset value msb xx x x x x x lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0 obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 118/201 parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode 10.5.3 general description the interface is externally connected to another device by two pins (see figure 54 ): tdo: transmit data output. when the transmitter and the receiver are disabled, the output pin returns to its i/o port configuration. when the transmitter and/or the receiver are enabled and nothing is to be transmitted, the tdo pin is at high level. rdi: receive data input is the serial data input. oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as frames comprising: an idle line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first a stop bit indicating that the frame is complete this interface uses two types of baud rate generator: a conventional type for commonly-used baud rates an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscilla tor frequencies. obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 119/201 figure 53. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe pe sci interrupt control cr1 r8 t8 scid m wake pce ps pie dr (data register) transmitter clock receiver clock receiver rate control transmitter rate control brr scp1 f cpu scp0 sct2 sct1 sct0 scr2 scr1 scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie cr2 read write transmit data register (tdr) transmit shift register received data register (rdr) received shift register tdo rdi obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 120/201 10.5.4 functional description the block diagram of the serial control interface, is shown in figure 53 . it contains 6 dedicated registers: two control registers (scicr1 and scicr2) a status register (scisr) a baud rate register (scibrr) an extended prescaler receiver register (scierpr) an extended prescaler transmitter register (scietpr) refer to the register descriptions in section 10.5.7 for the definitions of each bit. serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 register (see figure 53 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of ?1?s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving ?0?s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an extra ?1? bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 121/201 figure 54. word length programming transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 53 ). procedure select the m bit to define the word length select the desired baud rate using the scibrr and the scietpr registers set the te bit to assign the tdo pin to the alternate function and to send an idle frame as first transmission access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit break frame start bit extra ?1? data frame break frame extra ?1? data frame next data frame next data frame possible parity bit start bit obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 122/201 the tdre bit is set by hardware and it indicates: the tdr register is empty the data transfer is beginning the next data can be written in the scidr register without overwriting the previous data this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write instruction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write instruction to the scidr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shi ft register with a br eak character. the break frame length depends on the m bit (see figure 54 ). as long as the sbk bit is set, the sci send br eak frames to the tdo pi n. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a transmission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the scidr. obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 123/201 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least significant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) between the internal bus and the received shift register (see figure 53 ). procedure select the m bit to define the word length select the desired baud rate using the scibrr and the scierpr registers set the re bit, this enables the receiver which begins searching for a start bit when a character is received: the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register the error flags can be set if a frame error, noise or an overrun error has been detected during reception. clearing the rdrf bit is performed by th e following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci handles it as a framing error. idle character when an idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is received when rdrf has not been reset. data can not be transferred from the sh ift register to the rdr register as long as the rdrf bit is not cleared. when an overrun error occurs: the or bit is set the rdr content is not lost the shift register is overwritten an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register the or bit is reset by an access to the scisr register followed by a scidr register read operation. obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 124/201 noise error oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the nf flag is set. in the case of start bit detection, the nf flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). therefore, to prevent the nf flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples. when noise is detected in a frame: the nf flag is set at the rising edge of the rdrf bit data is transferred from the shift register to the scidr register no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf flag is reset by a scisr register read operation followed by a scidr register read operation. during reception, if a false start bit is detected (example, 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. there is no rdrf bit set for this fram e and the nf flag is set internally (not accessible to the user). this nf flag is acce ssible along with the rdrf bit when a next valid frame is received. note: if the application start bit is not long enough to match the above requirements, then the nf flag may get set due to the short start bit. in this case, the nf flag may be ignored by the application software when the first valid byte is received. see also noise error causes on page 129 . obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 125/201 figure 55. sci baud rate and extended prescaler block diagram transmitter clock receiver clock scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler receiver rate control transmitter rate control scibrr scp1 f cpu scp0 sct2 sct1 sct0 scr2 scr1 scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 126/201 framing error a framing error is detected when: the stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise. a break is received when the framing error is detected: the fe bit is set by hardware data is transferred from the shift register to the scidr register no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read operation followed by a scidr register read operation. conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: where: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits). all these bits are in the scibrr register (see baud rate register (scibrr) on page 136 ). example: if f cpu is 8 mhz (normal mode) and if pr = 13 and tr = rr = 1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is enabled. extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional baud rate generator retains industry standard software compatibility. the extended baud rate generator block diagram is described in figure 55 . the output clock rate sent to the transmitter or to the receiver is the output from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by setting the scietpr or scierpr register to a value other than zero. tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 127/201 the baud rates are calculated as follows : where: etpr = 1,..,255 (see extended transmit prescaler division register (scietpr) on page 137 ) erpr = 1,.. 255 (see extended receive prescaler division register (scierpr) on page 137 ) receiver muting and wake up feature in multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: none of the reception status bits can be set. all the receive interrupts are inhibited. a muted receiver may be awakened by one of the following two ways: by idle line detection if the wake bit is reset by address mark detection if the wake bit is set receiver wakes-up by idle li ne detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a ?1? as the most significant bit of a word, thus indicating that the message is an address. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. caution: in mute mode, do not write to the scicr2 register. if the sci is in mute mode during the read operation (rwu = 1) and an address mark wake up event occurs (rwu is reset) before the write operation, the rwu bit is set again by this write operation. consequently the address byte is lost and the sci is not woken up from mute mode. parity control parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the pce bit in the scicr1 register. depending on the frame length defined by the m bit, the possible sci frame formats are as listed in ta bl e 4 4 . tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*rr) f cpu obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 128/201 note: in case of wake up by an address mark, the msb bit of the data is taken into account and not the parity bit even parity the parity bit is calculated to obtain an even number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example, data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (ps bit = 0). odd parity the parity bit is calculated to obtain an odd number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. example, data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (ps bit = 1). transmission mode if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode if the pce bit is set then the interface checks if the received data byte has an even number of ?1s? if even parity is selected (ps = 0) or an odd number of ?1s? if odd parity is selected (ps = 1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is generated if pie is set in the scicr1 register. sci clock tolerance during reception, each bit is sampled 16 times. the majority of the 8th, 9th and 10th samples is considered as the bit value. for a valid bit detection, all the three samples should have the same value otherwise the noise flag (nf) is set. for example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value is ?1?, but the noise flag bit is set because the three samples values are not the same. consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. this means the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. table 44. frame formats (1) 1. legend: sb = start bit, stb = stop bit, pb = parity bit. m bit pce bit sci frame 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data pb | stb | obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 129/201 note: the internal samp ling clock of the microcontroller sa mples the pin value on every falling edge. therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. for example: if the baud rate is 15.625 kbaud (bit length is 64s), then the 8th, 9th and 10th sa mples are at 28s, 32s and 36s respectively (the first sample starti ng ideally at 0s). but if the falling edge of the internal clock occurs just before the pin value changes, the samples would then be out of sync by ~4s. this means the entire bit length must be at least 40s (36s for the 10th sample + 4s for synchronization with the internal sampling clock). clock deviation causes the causes which contribute to the total deviation are: d tra : deviation due to transmitte r error (local oscillator erro r of the transmitter or the transmitter is transmitting at a different baud rate). d quant : error due to the baud rate quantisation of the receiver d rec : deviation of the local oscillator of the receiver. this deviation can occur during the reception of one complete sci message assuming that the deviation has been compensated at the beginning of the message. d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the sci clock tolerance: d tra + d quant + d rec + d tcl < 3.75% noise error causes see also description of noise error in receiver on page 123 . start bit the noise flag (nf) is set during start bit reception if one of the following conditions occurs: 1. a valid falling edge is not de tected. a falling edge is consi dered to be valid if the 3 consecutive samples before the falling edge occu rs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a ?1?. 2. during sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a ?1?. therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag getting set. data bits the noise flag (nf) is set during normal data bit reception if the following condition occurs: during the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. the majority of the 8th, 9th and 10th samples is considered as the bit value. therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the noise flag being set. obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 130/201 figure 56. bit sampling in reception mode 10.5.5 low power modes 10.5.6 interrupts the sci interrupt events are connected to the same interrupt vector. these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). rdi line sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6/16 7/16 sampled values one bit time 7/16 table 45. effect of low power modes on sci mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting/receiving until halt mode is exited. table 46. sci interrupt control/wake-up capability interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie ye s n o transmission complete tc tcie received data ready to be read rdrf rie overrun error detected or idle line detected idle ilie parity error pe pie obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 131/201 10.5.7 sci registers status register (scisr) scisr reset value: 1100 0000 (c0h) 76543210 tdre tc rdrf idle or nf fe pe rrrrrrrr table 47. scisr register description bit bit name function 7tdre transmit data register empty this bit is set by hardware when th e content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie bit = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note: data are not transferred to th e shift register unless the tdre bit is cleared. 6tc transmission complete this bit is set by hardware when transmission of a frame containing data is complete. an interrupt is generated if tcie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the tran smission of a preamble or a break. 5 rdrf received data ready flag this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is generated if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: data are not received 1: received data are ready to be read 4idle idle line detect this bit is set by hardware when an idle line is detected. an interrupt is generated if the ilie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit is not set again until the rdrf bit is set (i.e. a new idle line occurs). obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 132/201 3or overrun error this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf = 1. an interrupt is generated if rie = 1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when the idle bit is set the rdr register content is not lost but the shift register is overwritten. 2nf noise flag this bit is set by hardware when noise is detected on a received frame. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: the nf bit does not generate an interrupt as it appears at the same time as the rdrf bit which itself generates an interrupt. 1fe framing error this bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: the fe bit does not generate an interrupt as it appears at the same time as the rdrf bit which itself generates an interrupt. if the word currently being transferre d causes both frame error and overrun error, it is transferred and only the or bit is set. 0pe parity error this bit is set by hardware when a parity error occurs in receiver mode. it is cleared by a software sequence (a read to the status register followed by an access to the scidr data register). an interrupt is generated if pie = 1 in the scicr1 register. 0: no parity error 1: parity error table 47. scisr register description (continued) bit bit name function obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 133/201 control register 1 (scicr1) scicr1 reset value: x000 0000 (x0b) 76543210 r8 t8 scid m wake pce ps pie r/w r/w r/w r/w r/w r/w r/w r/w table 48. scicr1 register description bit bit name function 7r8 receive data bit 8 this bit is used to store the 9th bit of the received word when m = 1. 6t8 transmit data bit 8 this bit is used to store the 9th bit of the transmitted word when m=1. 5scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped at the end of the current byte transfer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled 4m word length this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note: the m bit must not be modified during a data transfer (both transmission and reception). 3 wake wake up method this bit determines the sci wake up method, it is set or cleared by software. 0: idle line 1: address mark 2pce parity control enable this bit selects the hardware parity control (generation and detection). when the parity control is enabled, the computed parity is inserted at the msb position (9th bi t if m = 1; 8th bit if m = 0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmission). 0: parity control disabled 1: parity control enabled obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 134/201 control register 2 (scicr2) 1ps parity selection this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity is selected after the current byte. 0: even parity 1: odd parity 0pie parity interrupt enable this bit enables the interrupt capabi lity of the hardware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled scicr2 reset value: 0000 0000 (00h) 76543210 tie tcie rie ilie te re rwu sbk r/w r/w r/w r/w r/w r/w r/w r/w table 49. scicr2 register description bit bit name function 7tie transmitter interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre = 1 in the scisr register 6tcie transmission complete interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc = 1 in the scisr register 5rie receiver interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or = 1 or rdrf = 1 in the scisr register 4ilie idle line interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle = 1 in the scisr register table 48. scicr1 register description (continued) bit bit name function obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 135/201 data register (scidr) contains the received or transmitted data character, depending on whether it is read from or written to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (t dr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift register (see figure 53 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 53 ). 3te transmitter enable this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled note 1: during transmission, an ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. note 2: when te is set there is a 1 bit-time delay before the transmission starts. caution the tdo pin is free for general purpose i/o only when the te and re bits are both cleared (or if te is never set). 2re receiver enable this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit 1rwu receiver wake up this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (setting the rwu bit), the sci must receive some data first, other wise it cannot function in mute mode with wakeup by idle line detection. 0 sbk send break this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1? and then to ?0?, the transmitter sends a break word at the end of the current word. scidr reset value: undefined 76543210 dr[7:0] r/w table 49. scicr2 register description (continued) bit bit name function obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 136/201 baud rate register (scibrr) scibrr reset value: 0000 0000 (00h) 76543210 scp[1:0] sct[2:0] scr[2:0] r/w r/w r/w table 50. scibrr register description bit bit name function 7:6 scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: 00: pr prescaling factor = 1 01: pr prescaling factor = 3 10: pr prescaling factor = 4 11: pr prescaling factor = 13 5:3 sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with t he scp1 and scp0 bits define the total division applied to the bus cloc k to yield the transmit rate clock in conventional baud rate generator mode: 000: tr dividing factor = 1 001: tr dividing factor = 2 010: tr dividing factor = 4 011: tr dividing factor = 8 100: tr dividing factor = 16 101: tr dividing factor = 32 110: tr dividing factor = 64 111: tr dividing factor = 128 2:0 scr[2:0] sci receiver rate divisor these 3 bits, in conjunction with the scp[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode: 000: rr dividing factor = 1 001: rr dividing factor = 2 010: rr dividing factor = 4 011: rr dividing factor = 8 100: rr dividing factor = 16 101: rr dividing factor = 32 110: rr dividing factor = 64 111: rr dividing factor = 128 obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 137/201 extended receive prescaler division register (scierpr) allows setting of the extended prescaler rate division factor for the receive circuit. extended transmit prescaler division register (scietpr) allows setting of the external prescaler rate division factor for the transmit circuit. scierpr reset value: 0000 0000 (00h) 76543210 erpr[7:0] r/w table 51. scierpr register description bit bit name function 7:0 erpr[7:0] 8-bit extended receive prescaler register the extended baud rate generator is activated when a value different from 00h is stored in this regi ster. therefore the clock frequency issued from the 16 divider (see figure 55 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not used after a reset. scietpr reset value: 0000 0000 (00h) 76543210 etpr[7:0] r/w table 52. scietpr register description bit bit name function 7:0 etpr[7:0] 8-bit extended transmit prescaler register the extended baud rate generator is activated when a value different from 00h is stored in this regi ster. therefore the clock frequency issued from the 16 divider (see figure 55 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not used after a reset. obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 138/201 baud rate selection sci register map and reset values table 53. baud rate selection symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr)=128, pr=13 tr (or rr)= 32, pr=13 tr (or rr)= 16, pr=13 tr (or rr)= 8, pr=13 tr (or rr)= 4, pr=13 tr (or rr)= 16, pr= 13 tr (or rr)= 2, pr=13 tr (or rr)= 1, pr=13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz ~0.79% extended mode etpr (or erpr) = 35, tr (or rr) = 1, pr = 1 14400 ~14285.71 table 54. sci register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 0050h scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 pe 0 0051h scidr reset value msb xxx x x x x lsb x 0052h scibrr reset value scp1 0 scp0 0 sct2 0 sct1 0 sct0 0 scr2 0 scr1 0 scr0 0 0053h scicr1 reset value r8 x t8 0 scid 0 m 0 wake 0 pce 0 ps 0 pie 0 0054h scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 0055h scierpr reset value msb 000 0 0 0 0 lsb 0 0057h scipetpr reset value msb 000 0 0 0 0 lsb 0 obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 139/201 10.6 10-bit a/d converter (adc) 10.6.1 introduction the on-chip analog to digital converter (adc) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 10.6.2 main features 10-bit conversion up to 16 channels with multiplexed input linear successive approximation data register (dr) whic h contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 57 . figure 57. adc block diagram ch2 ch1 eoc spe 0ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 4 div 4 f adc f cpu d1 d0 adcdrl 0 1 00 0000 ch3 div 2 ed ad on obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 140/201 10.6.3 functional description the conversion is monotonic, meaning that the result never decreases if the analog input does not decrease and never increases if the analog input does not increase. if the input voltage (v ain ) is greater than v aref (high-level voltage reference) then the conversion result is ffh in the adcdrh register and 03h in the adcdrl register (without overflow indication). if the input voltage (v ain ) is lower than v ssa (low-level voltage reference) then the conversion result in the adcdrh an d adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conv ersion is stored in the adcdrh and adcdrl registers. the accuracy of the conversion is described in section 12: electrical characteristics . r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this results in a loss of accuracy due to leakage and sampling not being completed in the alloted time. a/d converter configuration the analog input ports must be configured as input, no pull-up, no interrupt. refer to section 9: i/o ports . using these pins as analog inputs does not affect th e ability of the port to be read as a logic input. in the adccsr register select the cs[3:0] bits to assign the analog channel to convert. starting the conversion in the adccsr register set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: the eoc bit is set by hardware the result is in the adcdr register a read to the adcdrh or a write to any bit of the adccsr register resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll the eoc bit 2. read the adcdrl register 3. read the adcdrh register. this clears eoc automatically note: the data is not latched, so both the low and the high data register must be read before the next conversion is complete, so it is recommended to disable interrupts while reading the conversion result. to read only 8 bits, perform the following steps: 1. poll the eoc bit 2. read the adcdrh register. this clears eoc automatically obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 141/201 changing the conversion channel the application can change channels during conversion. when software modifies the ch[3:0] bits in the adccsr register, the cu rrent conversion is stopped, the eoc bit is cleared, and the a/d converter starts converting the newly selected channel. 10.6.4 low power modes note: the a/d converter may be disabled by resetting the adon bit. this feature allows reduced power consumption when no conversion is needed. 10.6.5 interrupts none. 10.6.6 10-bit adc registers control/status register (adccsr) table 55. effect of low power modes on 10-bit adc mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time t stab (see section 12: electrical characteristics ) before accurate conversions can be performed. adccsr reset value: 0000 0000 (00h) 76543210 eoc speed adon 0 ch[3:0] r r/w r/w - r/w table 56. adccsr regi ster description bit bit name function 7eoc end of conversion this bit is set by hardware. it is cleared by hardware when software reads the adcdrh register or writ es to any bit of the adccsr register. 0: conversion is not complete 1: conversion complete 6 speed adc clock selection this bit is set and cleared by software. 0: f adc = f cpu /4 1: f adc = f cpu /2 5adon a/d converter on this bit is set and cleared by software. 0: disable adc and stop conversion 1: enable adc and start conversion obsolete product(s) - obsolete product(s) on-chip peripherals st7232axx-auto 142/201 data register (adcdrh) data register (adcdrl) 4 0 reserved, must be kept cleared. 3:0 ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert: 0000: channel pin = ain0 0001: channel pin = ain1 0010: channel pin = ain2 0011: channel pin = ain3 0100: channel pin = ain4 0101: channel pin = ain5 0110: channel pin = ain6 0111: channel pin = ain7 1000: channel pin = ain8 1001: channel pin = ain9 1010: channel pin = ain10 1011: channel pin = ain11 1100: channel pin = ain12 1101: channel pin = ain13 1110: channel pin = ain14 1111: channel pin = ain15 note: the number of channels is device dependent. refer to the section 2: pin description. adcdrh reset value: 0000 0000 (00h) 76543210 d[9:2] r table 57. adcdrh regi ster description bit bit name function 7:0 d[9:2] msb of converted analog value adcdrl reset value: 0000 0000 (00h) 76543210 0 d[1:0] -r table 56. adccsr register description (continued) bit bit name function obsolete product(s) - obsolete product(s) st7232axx-auto on-chip peripherals 143/201 adc register map and reset value table 58. adcdrl register description bit bit name function 7:2 0 reserved, must be kept cleared 1:0 d[1:0] lsb of converted analog value table 59. adc register map and reset values address (hex.) register label 7 6 5 4 3 2 1 0 0070h adccsr reset value eoc 0 speed 0 adon 00 ch3 0 ch2 0 ch1 0 ch0 0 0071h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0072h adcdrl reset value 0 0 0 0 0 0 d1 0 d0 0 obsolete product(s) - obsolete product(s) instruction set st7232axx-auto 144/201 11 instruction set 11.1 cpu addressing modes the cpu features 17 different addressing modes which can be classified in 7 main groups (see ta b l e 6 0 ). the cpu instruction set is designed to minimize the number of bytes required per instruction. to do so, most of the addressing modes may be subdivided in two sub-modes called long and short: long addressing mode is more powerful because it can use the full 64 kbyte address space, however it uses more bytes and more cpu cycles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory instructions use shor t addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 60. cpu addressing mode groups addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 obsolete product(s) - obsolete product(s) st7232axx-auto instruction set 145/201 table 61. cpu addressing mode overview mode syntax destination pointer address pointer size length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 00 00..ffff 00..ff word + 2 short indirect indexed ld a,([$1 0],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 obsolete product(s) - obsolete product(s) instruction set st7232axx-auto 146/201 11.1.1 inherent instructions all inherent instructions consis t of a single byte. the opcode fully specifies all the required information for the cpu to process the operation. 11.1.2 immediate instructions immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. table 62. inherent instructions inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles table 63. immediate instructions immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations obsolete product(s) - obsolete product(s) st7232axx-auto instruction set 147/201 11.1.3 direct instructions in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub-modes: direct instructions (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff addressing space. direct instructions (long) the address is a word, thus allowing 64 kbyte addressing space, but requires 2 bytes after the opcode. 11.1.4 indexed instructions (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte after the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte addressing space and requires 2 bytes after the opcode. 11.1.5 indirect instr uctions (short, long) the required data byte to do the operation is found by its memory address, located in memory (pointer). the pointer address follows the opcode. the indirect addressing mode consists of two sub- modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. obsolete product(s) - obsolete product(s) instruction set st7232axx-auto 148/201 11.1.6 indirect indexed instructions (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (x or y) with a pointer value located in memory. the pointer address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 64. instructions supporting direct, i ndexed, indirect and indirect indexed addressing modes long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/substraction operations bcp bit compare table 65. short instructions and functions short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine obsolete product(s) - obsolete product(s) st7232axx-auto instruction set 149/201 11.1.7 relative mode instruct ions (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub-modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. 11.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustra ted in the following table: table 66. relative mode instructions (direct and indirect) available relative direct/i ndirect instructions function jrxx conditional jump callr call relative table 67. instruction groups load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf obsolete product(s) - obsolete product(s) instruction set st7232axx-auto 150/201 11.3 using a pre-byte the instructions are described with one to four opcodes. in order to extend the number of available opcodes for an 8-bit cpu (256 opcodes), three different prebyte opcodes are defined. these prebytes modify the meaning of the instruction they precede. the whole instruction becomes: these prebytes enable instructions in y as well as indirect addressing modes to be implemented. they precede the opcode of the instructions in x or the instructions using direct addressing mode. the prebytes are: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one pix 92 replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode it also changes an instruction using x indexed addressing mode to an instruction using indirect x indexed addressing mode piy 91 replace an instruction using x indirect indexed addressing mode by a y one obsolete product(s) - obsolete product(s) st7232axx-auto instruction set 151/201 table 68. instruction set overview mnemo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. int pin = 1 (ext. int pin high) jril jump if ext. int pin = 0 (ext. int pin low) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= obsolete product(s) - obsolete product(s) instruction set st7232axx-auto 152/201 jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x, a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg and zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z table 68. instruction set overview (continued) mnemo description function/example dst src i1 h i0 n z c obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 153/201 12 electrical characteristics 12.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 12.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 12.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd = 5v. they are given only as design guidelines and are not tested. 12.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 58 . figure 58. pin loading conditions c l st7 pin obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 154/201 12.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 59 . figure 59. pin input voltage 12.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 12.2.1 voltage characteristics vin st7 pin table 69. voltage characteristics symbol ratings maximum value unit v dd - v ss supply voltage 6.5 v v pp - v ss programming voltage 13 v in (1)(2) 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of t he i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operat ion, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k ? for reset , 10k ? for i/os). for the same reason, unused i/o pins must not be directly tied to v dd or v ss . 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in st7232axx-auto electrical characteristics 157/201 12.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consumption, the two current values must be added (except for halt mode for which the clock is stopped). 12.4.1 current consumption table 73. current consumption symbol parameter conditions flash devices rom devices unit typ max (1) 1. data based on characterization results, tested in production at v dd max. and f cpu max. typ max (1) i dd supply current in run mode (2) 2. measurements are done in the following conditions: - progam executed from ram, cpu running with ram access. the increase in consumption when executing from flash is 50%. - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in reset state. - clock input (osc1) driven by external square wave. - in slow and slow wait mode, f cpu is based on f osc divided by 32. to obtain the total current consumption of the device, add the clock source ( section 12.5.3 ) and the peripheral power consumption ( section 12.4.3 ). f osc = 2mhz, f cpu =1mhz f osc = 4mhz, f cpu =2mhz f osc = 8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 1 1.4 2.4 4.4 2.3 3.5 5.3 7.0 1.3 2.0 3.6 7.1 2.0 3.0 5 10 ma supply current in slow mode (2) f osc = 2mhz, f cpu = 62.5khz f osc = 4mhz, f cpu = 125khz f osc = 8mhz, f cpu = 250khz f osc =16mhz, f cpu = 500khz 0.48 0.53 0.63 0.80 1 1.1 1.2 1.4 0.6 0.7 0.8 1.1 1.8 2.1 2.4 3.0 ma supply current in wait mode (2) f osc = 2mhz, f cpu =1mhz f osc = 4mhz, f cpu =2mhz f osc = 8mhz, f cpu =4mhz f osc =16mhz, f cpu =8mhz 0.6 0.9 1.3 2.3 1.8 2.2 2.6 3.6 1 1.5 2.5 4.5 1.3 2.0 3.3 6 ma supply current in slow wait mode (2) f osc = 2mhz, f cpu = 62.5khz f osc = 4mhz, f cpu = 125khz f osc = 8mhz, f cpu = 250khz f osc =16mhz, f cpu = 500khz 430 470 530 660 950 1000 1050 1200 70 100 200 350 200 300 600 1200 a supply current in halt mode (3) 3. all i/o pins in push-pull 0 mode (when applicable) with a static value at v dd or v ss (no load). data based on characterization results, tested in production at v dd max. and f cpu max. -40c t a +85c <1 10 <1 10 a -40c t a +125c 5 50 <1 50 supply current in active halt mode (4) 4. data based on characterisation results , not tested in production. all i/o pins in push-pull 0 mode (when applicable) with a static value at v dd or v ss (no load); clock input (osc1) driven by external square wave. to obtain the total current consumption of th e device, add the clock source consumption ( section 12.5.3 ). f osc =2mhz f osc =4mhz f osc =8mhz f osc =16mhz 60 100 180 340 160 200 300 500 22 44 86 170 30 60 120 300 a obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 158/201 power consumption vs f cpu : flash devices figure 61. typical i dd in run mode figure 62. typical i dd in slow mode 0 1 2 3 4 5 6 3 3. 3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5 .7 6 vdd (v) idd (ma) 2mhz 4mhz 8mhz 16mhz 0 0.2 0.4 0.6 0.8 1 1.2 3 3 .3 3.6 3.9 4.2 4.5 4 .8 5 .1 5.4 5.7 6 vdd (v) idd (ma) 2mhz 4mhz 8mhz 16mhz obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 159/201 figure 63. typical i dd in wait mode figure 64. typ. i dd in slow wait mode 12.4.2 supply and clock managers the previous current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consumption, the two current values must be added (except for halt mode). 0 0.5 1 1.5 2 2.5 3 3.5 3 3 . 3 3.6 3.9 4 . 2 4 . 5 4.8 5.1 5.4 5 . 7 6 vdd (v) idd (ma) 2mhz 4mhz 8mhz 16mhz 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 3 3 . 3 3. 6 3.9 4.2 4.5 4.8 5.1 5.4 5. 7 6 vdd (v) idd (ma) 2mhz 4mhz 8mhz 16mhz table 74. supply current of clock sources symbol parameter conditions typ max unit i dd(res) supply current of resonator oscillator (1)(2) 1. data based on characterization results done with the external components specified in section 12.5.3 , not tested in production. 2. as the oscillator is based on a current source, the cons umption does not depend on the voltage. see section 12.5.3 on page 162 a i dd(pll) pll supply current v dd = 5v 360 a obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 160/201 12.4.3 on-chip peripherals 12.5 clock and timing characteristics subject to general operating conditions for v dd , f cpu , and t a . 12.5.1 general timings table 75. on-chip peripherals symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current (1) 1. data based on a differential i dd measurement between reset configur ation (timer counter running at f cpu /4) and timer counter stopped (only timd bit set). data valid for one timer. t a =25c, f cpu = 4mhz, v dd =5.0v 50 a i dd(spi) spi supply current (2) 2. data based on a differential i dd measurement between reset configurat ion (spi disabled) and a permanent spi master communication at maximum speed (data se nt equal to 55h). this measurement includes the pad toggling consumption. 400 i dd(sci) sci supply current (3) 3. data based on a differential i dd measurement between sci low power state (scid=1) and a permanent sci data transmit sequence. i dd(adc) adc supply current when converting (4) 4. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. table 76. general timings symbol parameter conditions min typ (1) 1. data based on typical application software. max unit t c(inst) instruction cycle time 2312t cpu f cpu = 8mhz 250 375 1500 ns t v(it) interrupt reaction time (2) t v(it) = ? t c(inst) + 10 2. time measured between interrupt event and interrupt vector fetch. ? t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 10 22 t cpu f cpu = 8mhz 1.25 2.75 s obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 161/201 12.5.2 external clock source figure 65. typical application with an external clock source table 77. external clock source symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage see figure 65 v dd - 1 v dd v v osc1l osc1 input pin low level voltage v ss v ss + 1 t w(osc1h) t w(osc1l) osc1 high or low time (1) 1. data based on design simulation and/or technology characteristics, not tested in production. 5 ns t r(osc1) t f(osc1) osc1 rise or fall time (1) 15 i lkg osc1 input leakage current v ss v in v dd 1 a osc1 osc2 f osc external clock source st72xxx not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i lkg 90% 10% obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 162/201 12.5.3 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possibl e to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to t he crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). figure 66. typical application with a crystal or ceramic resonator table 78. oscillator parameters symbol parameter conditions min max unit f osc oscillator frequency (1) 1. the oscillator selection can be optimized in terms of supply current using a hi gh quality resonator with small r s value. refer to crystal/ceramic re sonator manufacturer for more details. lp: low power oscillator mp: medium power oscillator ms: medium speed oscillator hs: high speed oscillator 1 >2 >4 >8 2 4 8 16 mhz r f feedback resistor (2) 2. data based on characterisation results, not tested in production. 20 40 k ? c l1 c l2 recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (r s ) r s = 200 ? lp oscillator r s = 200 ? mp oscillator r s = 200 ? ms oscillator r s = 100 ? hs oscillator 22 22 18 15 56 46 33 33 pf i 2 osc2 driving current v in =v ss lp oscillator mp oscillator ms oscillator hs oscillator 80 160 310 610 150 250 460 910 a osc2 osc1 f osc c l1 c l2 i 2 r f st72xxx resonator when resonator with integrated capacitors obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 163/201 12.5.4 pll characteristics the user must take the pll jitter into account in the application (for example in serial communication or sampling of high frequency signals). the pll jitter is a periodic effect, which is integrated over several cpu cycles. therefore the longer the period of the application signal, the less it is impacted by the pll jitter. figure 67 shows the pll jitter integrated on application signals in the range 125khz to 2mhz. at frequencies of less than 125khz, the jitter is negligible. figure 67. integrated pll jitter vs signal frequency 1. measurement conditions: f cpu =8mhz. table 79. examples of typical resonators oscil. reference (1) 1. resonators all have different characteri stics. contact the manufacturer to obtai n the appropriate values of external components and to verify oscillator performance. freq. characteristic (2) 2. resonator characterist ics given by the ceramic resonator manufacturer. c l1 [pf] c l2 [pf] t su(osc) [ms] (3) 3. t su(osc) is the typical oscillator start-up time measured between v dd = 2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (< 50 s). ceramic lp murata csa2.00mg 2mhz ? f osc = [0.5% tolerance ,0.3% ? ta , 0.3% aging , x.x% correl ] 22 22 4 mp csa4.00mg 4mhz ? f osc = [0.5% tolerance ,0.3% ? ta , 0.3% aging , x.x% correl ] 22 22 2 ms csa8.00mtz 8mhz ? f osc = [0.5% tolerance ,0.5% ? ta , 0.3% aging , x.x% correl ] 33 33 1 hs csa16.00mxz040 (4) 4. 3rd overtone resonators require specific validation by the resonator manufacturer. 16mhz ? f osc = [0.5% tolerance ,0.3% ? ta , 0.3% aging , x.x% correl ] 33 33 0.7 table 80. pll characteristics symbol parameter conditions min typ max unit f osc pll input frequency range 2 4 mhz ? f cpu /f cpu instantaneous pll jitter (1) 1. data characterized but not tested. f osc = 4 mhz. 0.7 2 % 0 0.2 0.4 0.6 0.8 1 1.2 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz application frequency +/-jitter (%) ma x typ obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 164/201 12.6 memory characteristics 12.6.1 ram and hardware registers 12.6.2 flash memory table 81. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware register s (only in halt mode). not tested in production. halt mode (or reset) 1.6 v table 82. characteristics of dual voltage hdflash memory dual voltage hdflash memory symbol parameter conditions min (1) 1. data based on characterization results, not tested in production. typ max (1) unit f cpu operating frequency read mode 0 8 mhz write/erase mode 1 8 v pp programming voltage (2) 2. v pp must be applied only during the programming or eras ing operation and not permanently for reliability reasons. 4.5v v dd 5.5v 11.4 12.6 v i dd supply current (3) 3. data based on simulation results, not tested in production. write/erase <10 a i pp v pp current (3) read (v pp = 12v) 200 a write/erase 30 ma t vpp internal v pp stabilization time 10 s t ret data retention time t a = 55c 20 years n rw write erase cycles t a = 85c 100 cycles t prog t erase programming or erasing temperature range -40 25 85 c obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 165/201 12.7 electromagnetic compat ability (emc) characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 12.7.1 functional electromagn etic susceptibility (ems) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic ev ents until a failure occurs (indicated by the leds). esd: electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000 - 4 - 2 standard. ftb: a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000 - 4 - 4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forc ing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 166/201 12.7.2 electromagnetic interference (emi) based on a simple application running on the product (toggling two leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the boar d and the loading of each pin. table 83. electromagnetic test results symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance rom device, v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000 - 4 - 2 4a flash device, v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000 - 4 - 2 4b v fftb fast transient voltage burst limits to be applied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000 - 4 - 4 4a table 84. emi emissions (1) 1. refer to application note an1709 for data on other package types sym. parameter cond. device/package monitored frequency band max vs. [f osc /f cpu ] unit 8/4mhz 16/8mhz s emi peak level (2) 2. data based on characterization results, not tested in production v dd = 5v, t a = +25c conforming to sae j 1752/3 flash/lqfp32 0.1mhz to 30mhz 25 27 dbv 30mhz to 130mhz 30 36 130mhz to 1ghz 18 23 sae emi level 3.0 3.5 - rom/lqfp32 (3) 3. under completion 0.1mhz to 30mhz 25 27 dbv 30mhz to 130mhz 30 36 130mhz to 1ghz 18 23 sae emi level 3.0 3.5 - 8k flash/lqfp44 0.1mhz to 30mhz 12 18 dbv 30mhz to 130mhz 19 25 130mhz to 1ghz 15 22 sae emi level 3 3.5 - 8k rom/lqfp44 0.1mhz to 30mhz 12 15 dbv 30mhz to 130mhz 23 26 130mhz to 1ghz 15 20 sae emi level 3.0 3.5 - obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 167/201 12.7.3 absolute maximum rati ngs (electrical sensitivity) based on two different tests (esd and lu) usin g specific measurement methods, the device is stressed in order to determine its perfo rmance in terms of electrical sensitivity. electro-static discharge (esd) electro-static discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the aec-q100-002/003/011 standard. for more details, refer to the application note an1181. static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/0 pin these tests are compliant with eia/jesd 78a and aec-q100/004 ic latch-up standards. table 85. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c conforming to aec-q100- 002 h1c 2000 v v esd(mm) electro-static discharge voltage (machine model) t a = +25c conforming to aec-q100- 003 m2 200 v esd(cdm) electro-static discharge voltage (charged device model) t a = +25c conforming to aec-q100- 011 c3b > 500 to 750 with corner pins > 750 table 86. latch up results symbol parameter conditions class lu static latch-up class t a = +125c conforming to jesd 78a and aec-q100/004 ii level a obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 168/201 12.8 i/o port pin characteristics 12.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. table 87. i/o general port pin characteristics symbol parameter conditions min typ max unit v il input low level voltage (standard voltage devices) (1) 0.3 x v dd v v ih input high level voltage (1) 0.7 x v dd v v hys schmitt trigger voltage hysteresis (2) 0.7 i inj(pin) (3) injected current on flash device pin pb0 v dd =5v 0+4 ma injected current on other i/o pins 4 i inj(pin) (3) total injected current (sum of all i/o and control pins) 25 i lkg input leakage current v ss v in v dd 1 a i s static current cons umption induced by each floating input pin floating input mode (4)(5) 200 r pu weak pull-up equivalent resistor (6) v in = v ss, v dd =5v 50 120 250 k ? c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time (1) c l = 50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time (1) 25 t w(it)in external interrupt pulse time (7) 1t cpu 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switchin g levels. based on characterization results, not tested. 3. when the current limitation is not possible, the v in maximum must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics st7232axx-auto 170/201 12.8.2 output driving current subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 70. typical v ol at v dd = 5v (std. ports) table 88. output driving current symbol parameter conditions min max unit v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 70 ) v dd =5v i io =+5ma 1.2 v i io =+2ma 0.5 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 71 and figure 73 ) i io =+20ma, t a 85c t a > 85c 1.3 1.5 i io =+8ma 0.6 v oh (2) 2. the i io current sourced must always respect the absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins do not have v oh . output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 72 and figure 75 ) i io =-5ma, t a 85c t a > 85c v dd - 1.4 v dd - 1.6 i io =-2ma v dd - 0.7 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.005 0.01 0.015 ii o(a ) vol (v) at vdd=5v ta = 14 0c " ta = 95 c ta = 25 c ta = -45 c 51015 i io (ma) obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 171/201 figure 71. typ. v ol at v dd = 5v (high-sink ports) figure 72. typical v oh at v dd =5v figure 73. typical v ol vs. v dd (std. ports) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.01 0.02 0.03 ii o (a) vol(v) at vdd=5v ta= 140c ta= 95 c ta= 25 c ta= -45c 10 20 30 i io (ma) 2 2.5 3 3.5 4 4.5 5 5.5 -0.01 -0.008 -0.006 -0.004 -0.002 0 ii o ( a ) vdd-voh (v) at vdd=5v v dd= 5v 140c min v dd= 5v 95c min v dd= 5v 25c min v dd= 5v -45c min -10 -8 -6 -4 -2 0 i io (ma) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at iio=5ma ta= -4 5c ta= 25c ta= 95c ta= 140c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 2 2.5 3 3.5 44.5 55.5 6 vdd(v) vol(v) at iio=2ma ta=-45c ta=25c ta=95c ta=140c obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 172/201 figure 74. typical v ol vs. v dd (high-sink ports) figure 75. typical v oh vs. v dd 0 0.1 0.2 0.3 0.4 0.5 0.6 22.533.544.555.56 vdd(v) vol(v) at iio=8ma ta= 140c ta=95c ta=25c ta=-45c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 2 2.5 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at iio=20ma ta= 140c ta =95 c ta =25 c ta=-45c 0 1 2 3 4 5 6 22.533.544.555.56 vdd(v) vdd-voh(v) at iio=-5m a ta= -45c ta= 25c ta= 95c ta= 140c 2 2.5 3 3.5 4 4.5 5 5.5 22.5 33.544.555.56 vdd(v) vdd-voh(v) at iio=-2ma ta=-45c ta= 25c ta= 95c ta= 140c obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 173/201 12.9 control pin characteristics 12.9.1 asynchronous reset pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 76. reset pin protection 1. the reset network protects t he device against parasitic resets. 2. the output of the external reset circuit must have an open-dra in output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (watchdog). 3. 3. whatever the reset source is (internal or exte rnal), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 12.9.1 . otherwise the reset is not taken into account internally. 4. 4. because the reset circuit is designed to allo w the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin (by an external pull-up for example) is less than the absolute maximum value specified for i inj(reset) in section 12.2.2 on page 155 . table 89. asynchronous reset pin symbol parameter conditions min typ max unit v hys schmitt trigger voltage hysteresis (1) 2.5 v il input low level voltage (2) 0.16 x v dd v v ih input high level voltage (2) 0.85 x v dd v ol output low level voltage (3) v dd =5v i io = +2ma 0.2 0.5 i io driving current on reset pin 2 ma r on weak pull-up equivalent resistor vdd = 5v 20 30 120 k ? t w(rstl)out generated reset pulse duration internal reset sources 20 30 42 (4) s t h(rstl)in external reset pulse hold time (5) 2.5 s t g(rstl)in filtered glitch duration (6) 200 ns 1. hysteresis voltage between schmitt trigger switching levels. 2. data based on characterization results, not tested in production. 3. the i io current sunk must always respect the absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 4. data guaranteed by design, not tested in production. 5. to guarantee the reset of the device, a mi nimum pulse has to be applied to the reset pin. all short pulses applied on the reset pin with a duration below t h(rstl)in can be ignored. 6. the reset network (the resistor and two capacitors) protec ts the device against parasitic resets, especially in noisy environments. 0.01f reset circuit user external required st72xxx pulse generator filter r on v dd watchdog internal reset obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 174/201 12.9.2 iccsel/v pp pin subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 77. two typical applications with iccsel/v pp pin 1. when icc mode is not required by the application iccsel/v pp pin must be tied to v ss . 12.10 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to section 9: i/o ports for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). data based on design simulation and/or characterisation results, not tested in production. 12.10.1 16-bit timer table 90. iccsel/v pp pin characteristics symbol parameter conditions min max unit v il input low level voltage (1) 1. data based on design simulation and/or technology characteristics, not tested in production. flash versions v ss 0.2 v rom versions v ss 0.3 x v dd v ih input high level voltage (1) flash versions v dd - 0.1 12.6 rom versions 0.7 x v dd v dd i lkg input leakage current v in =v ss 1 ua iccsel/v pp st72xxx 10k ? programming tool v pp st72xxx table 91. 16-bit timer symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2 f cpu = 8mhz 250 ns f ext timer external clock frequency 0 f cpu /4 mhz f pwm pwm repetition rate 0 f cpu /4 res pwm pwm resolution 16 bit obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 175/201 12.11 communication interface characteristics 12.11.1 spi (serial peripheral interface) subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. data based on design simulation and/or characterisation results, not tested in production. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate functi on capability released. in this case, the pin status depends on the i/o port configuration. refer to section 9: i/o ports for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). table 92. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 = 0.0625 f cpu /4 = 2 mhz slave f cpu =8mhz 0 f cpu /2 = 4 t r(sck) t f(sck) spi clock rise and fall time see table 2: device pin description t su(ss ) (1) 1. data based on design simulation and/or charac terization results, not tested in production ss setup time (2) 2. depends on f cpu . for example, if f cpu = 8 mhz, then t cpu =1/f cpu = 125ns and t su (ss ) = 175ns. slave 120 ns t h(ss ) (1) ss hold time 120 t w(sckh) (1) t w(sckl) (1) sck high and low time master slave 100 90 t su(mi) (1) t su(si) (1) data input setup time master slave 100 100 t h(mi) (1) t h(si) (1) data input hold time master slave 100 100 t a(so) (1) data output access time slave 0 120 t dis(so) (1) data output disable time 240 t v(so) (1) data output valid time slave (after enable edge) 90 t h(so) (1) data output hold time 0 t v(mo) (1) data output valid time master (after enable edge) 120 t h(mo) (1) data output hold time 0 obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 176/201 figure 78. spi slave ti ming diagram with cpha = 0 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. figure 79. spi slave ti ming diagram with cpha = 1 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha = 0 mosi input miso output cpha = 0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a (so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out see note 2 cpol = 0 cpol = 1 t su(ss ) t h(ss) t dis(so) t h(so) see note 2 bit1 in ss input sck input cpha = 1 mosi input miso output cpha = 1 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out cpol = 0 cpol = 1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 see note 2 t c(sck) hz t v(so) msb in lsb in bit1 in obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 177/201 figure 80. spi master timing diagram 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capabi lity released. in this case, the pin status depends of the i/o port configuration. t su(mi) t h(mo) t v(mo) ss input t c(sck) sck input cpha = 0 cpha = 0 cpha=1 cpha = 1 cpol = 0 cpol = 1 cpol=0 cpol = 1 mosi output miso input seenote2 msb out bit6 out lsb out see note 2 msb in bit6 in lsb in t h(mi) t w(sckh) t w(sckl) t r(sck) t f(sck) obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 178/201 12.12 10-bit adc characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 81. r ain max. vs f adc with c ain =0pf 1. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (3pf). a high c parasitic value downgrades conversion a ccuracy. to remedy this, f adc should be reduced. table 93. 10-bit adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency 0.4 2 mhz v aref analog reference voltage 0.7 * v dd v aref v dd 3.8 v dd v v ain conversion voltage range (1) v ssa v aref i lkg input leakage current for analog input (2) -40c t a + 85c 250 na +85c < t a + 125c 1 a r ain external input impedance see figure 81 and figure 82 k ? c ain external capacitor on analog input pf f ain variation freq. of analog input signal hz c adc internal sample and hold capacitor 12 pf t adc conversion time (sample + hold) f cpu = 8mhz, speed = 0 f adc =2mhz 7.5 s t adc ? no of sample capacitor loading cycles ? no. of hold conversion cycles 4 11 1/f adc 1. any added external serial resistor downgrades the adc accuracy (espec ially for resistance greater than 10k ? ). data based on characterization results, not tested in production. 2. injecting negative current on adjacent pins may result in in creased leakage currents. softwar e filtering of the converted analog value is recommended. 0 5 10 15 20 25 30 35 40 45 0103070 c parasitic (pf) max. r ain (kohm) 2 m hz 1 m h z obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 179/201 figure 82. recommended c ain and r ain values 1. this graph shows that depending on the input signal variation (f ain ), c ain can be increased for stabilization time and decreased to allow the use of a larger serial resistor (r ain) . figure 83. typical a/d converter application 12.12.1 analog power supp ly and reference pins depending on the mcu pin count, the package may feature separate v aref and v ssa analog power supply pins. these pins supply power to the a/d converter cell and function as the high and low reference voltages for the conversion. in some packages, v aref and v ssa pins are not available (refer to section 2: pin description on page 19 ). in this case the analog supply and reference pads are internally bonded to the v dd and v ss pins. separation of the digital and analog power pins allow board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see section 12.12.2: general pcb design guidelines on page 180 ). 0. 1 1 10 100 1000 0. 01 0. 1 1 10 f ain (khz) max. r ain (kohm) cain 10 nf cain 22 nf cain 47 nf ainx st72xxx v dd i lkg v t 0.6v v t c adc 12pf v ain r ain 10-bit a/d conversion 2k ?( max ) c ain 0.6v obsolete product(s) - obsolete product(s) electrical characteristics st7232axx-auto 180/201 12.12.2 general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to shield the noise-sensitive, analog physical interface from noise-generating cmos logic signals. use separate digital and analog planes. the analog ground plane should be connected to the digital ground plane via a single point on the pcb. filter power to the analog power planes. it is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1f and optionally, if needed 10pf capacitors as close as possible to the st7 power supply pins and a 1 to 10f capacitor close to the power source (see figure 84 ). the analog and digital power supplies should be connected in a star nework. do not use a resistor, as v aref is used as a reference voltage by the a/d converter and any resistance would cause a voltage drop and a loss of accuracy. properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital outputs on the same i/o port as the a/d input being converted. figure 84. power supply filtering v ss v dd v dd v aref v ssa power source supply st7 digital noise filtering external noise filtering 1 to 10f 0.1f 0.1f st72xxx obsolete product(s) - obsolete product(s) st7232axx-auto electrical characteristics 181/201 12.12.3 adc accuracy figure 85. adc accura cy characteristics 1. legend: e t = total unadjusted error: maximum deviation between the actual and the ideal transfer curves e o = offset error: deviation between the firs t actual transition and the first ideal one e g = gain error: deviation between the last ideal transition and the last actual one e d = differential linearity error: maximum devi ation between actual steps and the ideal one e l = integral linearity error: maximum deviation between any actual transition and the end point correlation line table 94. adc accuracy with v dd =5.0v symbol parameter conditions typ max (1) 1. data based on characterization results, monitored in production to guarantee 99.73% within max value from -40c to 125c ( 3 distribution limits). unit |e t | total unadjusted error (2) 2. adc accuracy vs. negative injection current: injecting negative current may reduce the accuracy of the conversion being performed on another analog input. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 12.8 does not affect the adc accuracy. cpu in run mode @ f adc =2 mhz. 46 lsb |e o | offset error (2) 35 |e g | gain error (2) 0.5 4.5 |e d | differential linearity error (2) 1.5 4.5 |e l | integral linearity error (2) 1.5 4.5 e o e g 1lsb ideal 1lsb ideal v aref v ssa ? 1024 -------------------------------------------- = v in (lsb ideal ) digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 10211022 1023 1024 (1) (2) e t e d e l (3) v aref v ssa (1) = example of an actual transfer curve (2) = ideal transfer curve (3) = end point correlation line obsolete product(s) - obsolete product(s) package characteristics st7232axx-auto 182/201 13 package characteristics 13.1 package mechanical data figure 86. 32-pin lqfp outline table 95. 32-pin lqfp mechanical data dim. mm inches min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 9.000 0.3543 d1 7.000 0.2756 e 9.000 0.3543 e1 7.000 0.2756 e 0.800 0.0315 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 h c l l1 b e a1 a2 a e e1 d d1 obsolete product(s) - obsolete product(s) st7232axx-auto package characteristics 183/201 figure 87. 44-pin lqfp outline table 96. 44-pin lqfp mechanical data dim. mm inches min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.000 0.0079 d 12.000 0.4724 d1 10.000 0.3937 e 12.000 0.4724 e1 10.000 0.3937 e 0.800 0.0315 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0236 a a2 a1 b e l1 l h c e e1 d d1 obsolete product(s) - obsolete product(s) package characteristics st7232axx-auto 184/201 13.2 thermal characteristics 13.3 soldering information in order to meet environmental requirements, st offers these devices in ecopack? pack- ages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack? specifications are available at www.st.com . compatibility ecopack? lqfp packages are fully compatible with lead (pb) containing soldering process (see application note an2034). table 97. thermal characteristics symbol ratings value unit r thja package thermal resistance (junction to ambient) lqfp32 lqfp44 70 52 c/w p d power dissipation (1) 1. the maximum power dissipation is obtained from the formula p d =(t j -t a )/r thja . the power dissipation of an application can be defined by th e user with the formula: p d =p int +p port where p int is the chip internal power (i dd x v dd ) and p port is the port power dissipati on depending on the ports used in the application. 500 mw t jmax maximum junction temperature (2) 2. the maximum chip-junction temperature is based on technology characteristics. 150 c table 98. soldering compatibility (wave and reflow soldering process) package plating material devices pb solder paste pb-free solder paste lqfp32 nipdau (nickel-palladium-gold) ye s ye s lqfp44 sn (pure tin) obsolete product(s) - obsolete product(s) st7232axx-auto device configuration and ordering information 185/201 14 device configuration and ordering information 14.1 introduction each device is available for production in user programmable versions (flash) as well as in factory coded versions (rom/fastrom). st7232a-auto are rom versions. st72p32a-auto devices are factory advanced service technique rom (fastrom) versions: they are factory-programmed hdflash devices. flash devices are shipped to customers with a default content (ffh), while rom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the customer using the option bytes while the rom devices are factory-configured. 14.2 flash devices 14.2.1 flash configuration 1. depends on device type as defined in table 102: package selection (opt7) on page 187 the option bytes allows the hardware configuration of the microcontroller to be selected. they have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 programming tool). the default content of the flash is fixed to ffh. to program directly the flash devices using icp, flash devices are shipped to customers with an internal clock source selected. in masked rom devices, the option bytes are fixed in hardware by the rom code (see option list). table 99. flash option bytes static option byte 0 s tatic option byte 1 7654321 0 7 6 543210 wdg reserved fmp_r pkg1 rstc osctype oscrange pll off haltsw 10210 default 1 1 1 1 1 1 1 1 see note 1 1 100111 obsolete product(s) - obsolete product(s) device configuration and ordering information st7232axx-auto 186/201 table 100. option byte 0 description bit bit name function 7 wdg halt watchdog reset on halt this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode 6wdg sw hardware or software watchdog this option bit selects the watchdog type 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) 5:1 - reserved, must be kept at default value 0fmp_r flash memory read-out protection read-out protection, when selected, pr ovides a protection against program memory content extraction and against write access to flash memory. erasing the option bytes when the fmp_ r option is selected causes the whole user memory to be erased first, and the device can be reprogrammed. refer to section 4.3.1: read-out protection on page 28 and the st7 flash programming reference manual for more details. 0: read-out protection enabled 1: read-out protection disabled table 101. option byte 1 description bit bit name function 7 pkg1 pin package selection bit this option bit selects the package (see ta b l e 1 0 2 ) note: on the chip, each i/o port has 8 pads. pads that are not bonded to external pins are in input pull-up configuration af ter reset. the configuration of these pads must be kept at reset state to avoid added current consumption. 6 rstc reset clock cycle selection this option bit selects the number of cpu cycles appl ied during the reset phase and when exiting halt mode. for resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time. 0: reset phase with 4096 cpu cycles 1: reset phase with 256 cpu cycles 5:4 osctype[1:0] oscillator type these option bits select the st7 main clock source type: 00: clock source = resonator oscillator 01: reserved 10: reserved 11: clock source = external source obsolete product(s) - obsolete product(s) st7232axx-auto device configuration and ordering information 187/201 14.2.2 flash ordering information the following ta b l e 1 0 3 serves as a guide for ordering. 3:1 oscrange[2:0] oscillator range when the resonator oscillator is selected, these option bits select the resonator oscillator current source corresponding to the frequency range of the used resonator. otherwise, these bits are used to select the normal frequency range. 000: typ. frequency range (lp) = >1~2mhz 001: typ. frequency range (mp) = >2~4mhz) 010: typ. frequency range (ms) = >4~8mhz) 011: typ. frequency range (hs) = >8~16mhz) 0pll off pll activation this option bit activates the pll which allows multiplication by two of the main input clock frequency. the pll must not be used with the internal rc oscillator. the pll is guaranteed only with an input frequency between 2 and 4mhz. 0: pll x2 enabled 1: pll x2 disabled caution: the pll can be enabled only if the ?osc range? (opt3:1) bits are configured to ?mp - 2~4mhz?. otherwis e, the device functionality is not guaranteed. caution 2: when the pll is used with an external clock signal, the clock signal must be available on the oscin pin before the reset signal is released. table 102. package selection (opt7) version selected package pkg1 jlqfp441 klqfp320 table 101. option byte 1 description (continued) bit bit name function table 103. flash user programmable device types order code (1) package flash memory (kbytes) temperature range st72f32ak1tare lqfp32 4k 40c +85c st72f32ak1tcre 40c +125c st72f32ak2tare 8k 40c +85c st72f32ak2tcre 40c +125c st72f32aj1tare lqfp44 4k8 40c +85c st72f32aj1tcre 40c +125c st72f32aj2tare 8k 40c +85c st72f32aj2tcre 40c +125c 1. r = tape and reel (left blank if tray) obsolete product(s) - obsolete product(s) device configuration and ordering information st7232axx-auto 188/201 figure 88. flash commercial product code structure 14.3 rom device ordering informat ion and transfer of customer code customer code is made up of the rom/fastrom contents and the list of the selected options (if any). the rom/fastrom contents are to be sent with the s19 hexadecimal file generated by the development tool. all unused bytes must be set to ffh. complete the appended st72p32a/st7232a (3.8 to 5.5v) microcontroller option list on page 191 to communicate the selected options to stmicroelectronics. refer to application note an1635 for information on the counter listing returned by st after code has been transferred. table 104: fastrom factory coded device types on page 189 and ta bl e 1 0 5 : ro m fa c t o r y coded device types on page 190 serve as guides for ordering. the stmicroelectronics sales organization will be pleased to prov ide detailed information on contractual points. caution: the readout protection binary value is inverted between rom and flash products. the option byte checksum differs between rom and flash. device package temp range r pinout prog mem e = lead-free (ecopack?) conditioning options r = tape and reel (left blank if tray) a = -40 to +85c c = -40 to +125c t = low profile quad flat pack 1=4 kbytes 2=8 kbytes k = 32 pins j = 44 pins st72f32a e obsolete product(s) - obsolete product(s) st7232axx-auto device configuration and ordering information 189/201 figure 89. fastrom commercial product code structure table 104. fastrom factory coded device types order code (1) 1. the two characters in parentheses which represent the pinout and program memory size are for reference only and are not visible in the final commercial product order code. ?xxx? represents the code name def ined by stmicroelectronics: it de notes the rom code, pinout and program memory size. r = tape and reel (left blank if tray) package flash memory (kbytes) temperature range st72p32a(k1)taxxxre lqfp32 4k 40c +85c st72p32a(k1)tcxxxre 40c +125c st72p32a(k2)taxxxre 8k 40c +85c st72p32a(k2)tcxxxre 40c +125c st72p32a(j1)taxxxre lqfp44 4k 40c +85c st72p32a(j1)tcxxxre 40c +125c st72p32a(j2)taxxxre 8k 40c +85c st72p32a(j2)tcxxxre 40c +125c device package xxx e = lead-free (ecopack?) conditioning options: r = tape and reel (left blank if tray) code name (defined by stmicroelectronics) (denotes rom code, pinout and program memory size) a = -40 to +85c b = -40 to +105c c = -40 to +125c t = low profile quad flat pack st72p32a r e temp range obsolete product(s) - obsolete product(s) device configuration and ordering information st7232axx-auto 190/201 figure 90. rom commercial product code structure table 105. rom factory coded device types order code (1) 1. the two characters in parentheses which represent the pinout and program memory size are for reference only and are not visible in the final commercial product order code. ?xxx? represents the code name def ined by stmicroelectronics: it de notes the rom code, pinout and program memory size. r = tape and reel (left blank if tray) package flash memory (kbytes) temperature range st7232a(k1)ta/xxxre lqfp32 4k 40c +85c st7232a(k1)tc/xxxre 40c +125c st7232a(k2)ta/xxxre 8k 40c +85c st7232a(k2)tc/xxxre 40c +125c st7232a(j1)ta/xxxre lqfp44 4k 40c +85c st7232a(j1)tc/xxxre 40c +125c st7232a(j2)ta/xxxre 8k 40c +85c st7232a(j2)tc/xxxre 40c +125c device package xxx e = lead-free (ecopack?) conditioning options: r = tape and reel (left blank if tray) code name (defined by stmicroelectronics) (denotes rom code, pinout and program memory size) a = -40 to +85c b = -40 to +105c c = -40 to +125c t = low profile quad flat pack st7232a r e temp range / obsolete product(s) - obsolete product(s) st7232axx-auto device configuration and ordering information 191/201 1. pll not supported with external clock source 2. the pll can be enabled only if the resonator is configured to ?m edium power: 2~4mhz? 3. the readout protection binary value is inverted between rom and flash products. the option byte checksum differs between rom and flash. st72p32a/st7232a (3.8 to 5.5v) microcontroller option list (last update: september 2007) customer: ..................................................................... address: ..................................................................... ..................................................................... contact: ..................................................................... phone no: ..................................................................... reference/rom or fastrom code: ............................... the fastrom/rom code name is assigned by stmicroelectronics. fastrom/rom code must be sent in .s19 fo rmat. .hex extension cannot be processed. device type/memory size/package (check only one option): ------------------------------------------------------------------------------------------------------------------------------- --------------- rom 4k 8k ------------------------------------------------------------------------------------------------------------------------------- --------------- lqfp32: [ ] st7232a(k1)t [ ] st7232a(k2)t lqfp44: [ ] st7232a(j1)t [ ] st7232a(j2)t ------------------------------------------------------------------------------------------------------------------------------- --------------- ------------------------------------------------------------------------------------------------------------------------------- --------------- fastrom 4k 8k ------------------------------------------------------------------------------------------------------------------------------- --------------- lqfp32: [ ] st72p32a(k1)t [ ] st72p32a(k2)t lqfp44: [ ] st72p32a(j1)t [ ] st72p32a(j2)t ------------------------------------------------------------------------------------------------------------------------------- --------------- conditioning (check only one option): lqfp packaged product [ ] tape and reel [ ] tray temperature range: [ ] a (-40c to +85c) [ ] b (-40c to +105c) [ ] c (-40c to +125c) special marking: [ ] no [ ] yes ".........................." (lqfp32 7 char., other pkg. 10 char. max) authorized characters are letters, digits, '.', '-', '/' and spaces only. clock source selection: [ ] resonator [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] external clock (1) pll (1)(2) : [ ] disabled [ ] enabled reset delay: [ ] 256 cycles [ ] 4096 cycles watchdog selection: [ ] software activation [ ] hardware activation watchdog reset on halt: [ ] reset [ ] no reset readout protection (3) : [ ] disabled [ ] enabled date ............................ signature ............................. obsolete product(s) - obsolete product(s) device configuration and ordering information st7232axx-auto 192/201 14.4 development tools 14.4.1 introduction development tools for the st7 microcontrollers include a complete range of hardware systems and software tools from stmicroelectronics and third-party tool suppliers. the range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 14.4.2 evaluation tool s and starter kits st offers complete, affordable starter kits and full-featured evaluation boards that allow you to evaluate microcontroller features and quickly start developing st7 applications. starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your application. st evaluation boards are open-design, embedded systems, which are developed and documented to serve as references for your application design. they include sample application software to help you demonstrate, learn about and implement your st7?s features. 14.4.3 development and debugging tools application development for st7 is supported by fully optimizing c compilers and the st7 assembler-linker toolchain, which are all seamlessly integrated in the st7 integrated development environments in order to facilit ate the debugging and fine-tuning of your application. the cosmic c compile r is available in a free version that outputs up to 16 kbytes of code. the range of hardware tools includes cost effective st7-dvp3 series emulators. these tools are supported by the st7 toolset from stmicroelectronics, which includes the stvd7 integrated development environment (ide) with high-level language debugger, editor, project manager and integrated programming interface. 14.4.4 programming tools during the development cycle, the st7-dvp3 and st7-emu3 series emulators and the rlink provide in-circuit programming capabilit y for programming the flash microcontroller on your application board. st also provides dedicated a low-cost dedicated in-circuit programmer, the st7-stick, as well as st7 socket boards which provide all the sockets required for programming any of the devices in a specific st7 subfamily on a platform that can be used with any tool with in- circuit programming capability for st7. for production programming of st7 devices, st?s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment. for additional ordering codes for spare parts, accessories and tools available for the st7 (including from third party manufacturers), refer to the online product selector at www.st.com/mcu. obsolete product(s) - obsolete product(s) st7232axx-auto device configuration and ordering information 193/201 14.4.5 socket and emulator adapter information for information on the type of socket that is supplied with the emulator, refer to the suggested list of sockets in ta b l e 1 0 7 . note: before designing the board layout, it is recommended to check the overall dimensions of the socket as they may be greater than the dimensions of the device. for footprint and other mechanical information about these sockets and adapters, refer to the manufacturer?s datasheet (www.ironwoodelectronics.com for lqfp32 7 x 7). 14.5 st7 application notes for all revelant application notes, refer to www.st.com. table 106. stmicroelectronics development tools supported products emulation programming st7 dvp3 series st7 emu3 series icc socket board emulator connection kit emulator active probe and teb st7232aj, st72f32aj st7mdt20- dvp3 st7mdt20- t44/dvp st7mdt20 j-emu3 st7mdt20 j-teb st7sb20 j/xx (1) 1. add suffix /eu, /uk, /us for t he power supply of your region. st7232ak, st72f32ak st7mdt20- dvp3 st7mdt20- t32/dvp table 107. suggested list of socket types device socket (supplied with st7mdt20j-emu3) emulator adapter (supplied with st7mdt20j-emu3) lqfp32 7 x 7 ironwood sf-qfe32sa-l-01 ironwood sk-uga06/32a-01 lqfp44 10 x10 yamaichi ic149- 044-*52-*5 yamaichi icp-044-5 obsolete product(s) - obsolete product(s) known limitations st7232axx-auto 194/201 15 known limitations 15.1 all flash and rom devices 15.1.1 safe connection of osc1/osc2 pins the osc1 and/or osc2 pins must not be left unconnected otherwise the st7 main oscillator may start and, in this configuration, co uld generate an f osc clock frequency in excess of the allowed maximum (>16mhz.), putting the st7 in an unsafe/undefined state. refer to section 6.4: multi-osc illator (mo) on page 37 . 15.1.2 external interrupt missed to avoid any risk of generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either ddr and or. any input signal edge during this period is not detected and does not generate an interrupt. this case can typically occur if the application refreshes the port configuration registers at intervals during runtime. workaround the workaround is based on software checking the level on the interrupt pin before and after writing to the pxor or pxddr registers. if there is a level change (depending on the sensitivity programmed for this pin) the interrup t routine is invoked using the call instruction with three extra push instructions before executing the interrupt routine (this is to make the call compatible with the iret instruction at the end of the interrupt service routine). but detection of the level change does not make sure that edge occurs during the critical one cycle duration and the interrupt has been missed. this may lead to occurrence of same interrupt twice (one hardware and another with software call). to avoid this, a semaphore is set to ?1? before checking the level change. the semaphore is changed to level '0' inside the interrupt routine. when a level change is detected, the semaphore status is checked and if it is ?1? this means that the last interrupt has been missed. in this case, the interrupt rout ine is invoked with the call instruction. there is another possible case that is, if writing to pxor or pxddr is done with global interrupts disabled (interrupt mask bit set). in this case, the semaphore is changed to ?1? when the level change is detected. detecting a missed interrupt is done after the global interrupts are enabled (interrupt mask bit reset) and by checking the status of the semaphore. if it is ?1? this means that the last interrupt was missed and the interrupt routine is invoked with the call instruction. to implement the workaround, the following software sequence is to be followed for writing into the pxor/pxddr registers. the example is for port pf1 with falling edge interrupt sensitivity. the software sequence is given for both cases (global interrupt disabled/enabled). obsolete product(s) - obsolete product(s) st7232axx-auto known limitations 195/201 case 1: writing to pxor or pxddr wi th global interrupts enabled: ld a,#01 ld sema,a; set the semaphore to '1' ld a,pfdr and a,#02 ld x,a; store the level before writing to pxor/pxddr ld a,#$90 ld pfddr,a ; write to pfddr ld a,#$ff ld pfor,a ; write to pfor ld a,pfdr and a,#02 ld y,a; store the level after writing to pxor/pxddr ld a,x; check for falling edge cp a,#02 jrne out tnz y jrne out ld a,sema ; check the semaphore status if edge is detected cp a,#01 jrne out call call_routine ; call the interrupt routine out:ld a,#00 ld sema,a .call_routine ; entry to call_routine push a push x push cc .ext1_rt ; entry to interrupt routine ld a,#00 ld sema,a iret case 2: writing to pxor or pxddr with global interrupts disabled: sim ; set the interrupt mask ld a,pfdr and a,#$02 ld x,a ; store the level before writing to pxor/pxddr ld a,#$90 ld pfddr,a ; write into pfddr ld a,#$ff ld pfor,a ; write to pfor ld a,pfdr and a,#$02 ld y,a ; store the level after writing to pxor/pxddr ld a,x ; check for falling edge cp a,#$02 jrne out tnz y jrne out ld a,#$01 ld sema,a ; set the semaphore to '1' if edge is detected obsolete product(s) - obsolete product(s) known limitations st7232axx-auto 196/201 rim ; reset the interrupt mask ld a,sema ; check the semaphore status cp a,#$01 jrne out call call_routine ; call the interrupt routine rim out:rim jp while_loop .call_routine ; entry to call_routine push a push x push cc .ext1_rt ; entry to interrupt routine ld a,#$00 ld sema,a iret 15.1.3 unexpected reset fetch if an interrupt request occurs while a ?pop cc? instruction is ex ecuted, the interrupt controller does not recognise the source of the interrupt and, by default, passes the reset vector address to the cpu. workaround to solve this issue, a ?pop cc? instruction must always be preceded by a ?sim? instruction. 15.1.4 clearing active interrupts outside interrupt routine when an active interrupt request occurs at the same time as the related flag is being cleared, an unwanted reset may occur. note: clearing the related interrupt mask does not generate an unwanted reset. concurrent interrupt context the symptom does not occur when the interrupts are handled normally, i.e. when: the interrupt flag is cleared within its own interrupt routine the interrupt flag is cleared within any interrupt routine the interrupt flag is cleared in any part of the code while this interrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following sequence: perform sim and rim operation before and after resetting an active interrupt request. example: sim reset interrupt flag rim obsolete product(s) - obsolete product(s) st7232axx-auto known limitations 197/201 nested interrupt context the symptom does not occur when the interrupts are handled normally, i.e. when: the interrupt flag is cleared within its own interrupt routine the interrupt flag is cleared within any interrupt routine with higher or identical priority leve the interrupt flag is cleared in any part of the code while this interrupt is disabled if these conditions are not met, the symptom can be avoided by implementing the following sequence: push cc sim reset interrupt flag pop cc 15.1.5 16-bit timer pwm mode in pwm mode, the first pwm pulse is missed after writing the value fffch in the oc1r register (oc1hr, oc1lr). it leads to either full or no pwm during a period, depending on the olvl1 and olvl2 settings. 15.1.6 timd set simultaneo usly with oc interrupt description if the 16-bit timer is disabled at the same ti me as the output compare event occurs, then the output compare flag gets locked and cannot be cleared before the timer is enabled again. impact on the application if output compare interrupt is enabled, then the output compare flag cannot be cleared in the timer interrupt routine. consequently the interrupt service routine is called repeatedly and the application gets stuck which causes the watchdog reset if enabled by the application. workaround disable the timer interrupt before disabling the timer. while enabling, first enable the timer, then the timer interrupts. perform the following to disable the timer: tacr1 or tbcr1 = 0x00h; // disable the compare interrupt tacsr | or tbcsr | = 0x40; // disable the timer perform the following to enable the timer again: tacsr & or tbcsr & = ~0x40; // enable the timer tacr1 or tbcr1 = 0x40; // enable the compare interrup obsolete product(s) - obsolete product(s) known limitations st7232axx-auto 198/201 15.1.7 sci wrong break duration description a single break characte r is sent by setting and resetting the sbk bit in the scicr2 register. in some cases, the break character may have a longer duration than expected: - 20 bits instead of 10 bits if m = 0 - 22 bits instead of 11 bits if m = 1. in the same way, as long as the sbk bit is se t, break characters are sent to the tdo pin. this may lead to generate one break more than expected. occurrence the occurrence of the problem is random and proportional to the baudrate. with a transmit frequency of 19200 baud (f cpu = 8mhz and scibrr = 0xc9), the wrong break duration occurrence is around 1%. workaround if this wrong duration is not compliant with th e communication protocol in the application, software can request that an idle line be generated before the break character. in this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. this can be ensured by temporarily disabling interrupts. the exact sequence is: disable interrupts reset and set te (idle request) set and reset sbk (break request) re-enable interrupts 15.1.8 39-pulse icc entry mode for flash devices, icc mode entry using st7 application clock (39 pulses) is not supported. external clock mode must be used (36 pulses). refer to the st7 flash programming reference manual. obsolete product(s) - obsolete product(s) st7232axx-auto known limitations 199/201 15.2 rom devices only 15.2.1 i/o port a and f configuration when using an external quartz crystal or ceramic resonator, a few f osc2 clock periods may be lost when the signal pattern in ta b l e 1 0 8 occurs . this is because this pattern causes the device to enter test mode and return to user mode after a few clock periods. user program execution and i/o status are not changed, only a few clock cycles are lost. this happens with either one of the following configurations (see also ta bl e 1 0 8 ): pa3 = 0, pf4 = 1, pf1 = 0 while pll option is disabled and pf0 is toggling. pa3 = 0, pf4 = 1, pf1 = 0, pf0 = 1 while pll option is enabled. as a consequence, for cycle-accurate operations, these configurations are prohibited in either input or output mode. workaround to avoid this occurring, it is recommended to connect one of these pins to gnd (pf4 or pf0) or v dd (pa3 or pf1). 15.2.2 external clock source with pll pll is not supported with external clock source. table 108. port a and f configuration pll pa3 pf4 pf1 pf0 clock disturbance off 0 1 0 toggling max. 2 clock cycles lost at each rising or falling edge of pf0 on 0 1 0 1 max. 1 clock cycle lost out of every 16 obsolete product(s) - obsolete product(s) revision history st7232axx-auto 200/201 16 revision history table 109. document revision history date revision changes 28-jan-2008 1 initial release obsolete product(s) - obsolete product(s) st7232axx-auto 201/201 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com obsolete product(s) - obsolete product(s) |
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